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| ics for communications dsp oriented pbx controller doc peb 20560 version 2.1 preliminary data sheet 11.97 h t t p : / / w w w . s i e m en s . d e / s em i c o nd uc t o r /
peb 20560 revision history: current version: preliminary data sheet 11.97 previous version: preliminary data sheet 03.97 page (in previous version) page (in current version) subjects (major changes since last revision) global interrupt status register (version 2.1) interrupt mask register for gpio (version 2.1) edition 11.97 published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1997. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered. peb 20560 table of contents page semiconductor group i-1 1997-11-01 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 doc features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.5 functional block diagram and system integration . . . . . . . . . . . . . . . 1-25 1.6 example for system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 2 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 elic0 and elic1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 general functions and device architecture . . . . . . . . . . . . . . . . . . . . 2-1 2.1.2 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.2.1 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.2.2 reset logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2.3 epic ? -1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.2.3.1 pcm-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.2.3.2 configurable interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.2.3.3 memory structure and switching . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.2.3.4 pre-processed channels, layer-1 support . . . . . . . . . . . . . . . . . . 2-4 2.1.2.3.5 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.1.2.4 sacco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.1.2.4.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.1.2.4.2 parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.1.2.4.3 fifo-structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.1.2.4.4 protocol support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.1.2.4.5 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.1.2.4.6 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.1.2.4.7 serial port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.1.2.4.8 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 2.1.2.5 d-channel arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 2.1.2.5.1 upstream direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 2.1.2.5.2 downstream direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 2.1.2.5.3 control channel delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2.1.2.5.4 d-channel arbiter co-operating with quat-s circuits . . . . . . . . 2-40 2.2 sidec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.3 multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.3.1 iom ? - and pcm-ports multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 2.3.1.1 iom ? multiplexer for iom ? -2 ports (cfi interfaces of epic) . . . . . 2-45 2.3.1.2 pcm-ports multiplexer for pcm highways . . . . . . . . . . . . . . . . . . . 2-46 2.3.2 multiplexers for signaling controllers . . . . . . . . . . . . . . . . . . . . . . . . 2-47 2.3.2.1 sacco-a0 and sacco-a1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 2.3.2.2 sacco-b0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 peb 20560 table of contents page semiconductor group i-2 1997-11-01 2.3.2.3 sacco-b1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 2.3.2.4 sidec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 2.3.3 elic1-ports multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 2.3.4 iom ? -multiplexer for dsp connection to epics . . . . . . . . . . . . . . . . 2-52 2.3.5 pcm/iom mux registers description . . . . . . . . . . . . . . . . . . . . . . . 2-53 2.3.5.1 pcm/iom mux mode register (mmode) . . . . . . . . . . . . . . . . . . . 2-53 2.3.5.2 cfi channel select 0 register (mcchsel0) . . . . . . . . . . . . . . . . 2-54 2.3.5.3 cfi channel select 1 register (mcchsel1) . . . . . . . . . . . . . . . . 2-55 2.3.5.4 cfi channel select 2 register (mcchsel2) . . . . . . . . . . . . . . . . 2-56 2.3.5.5 pcm channel select 0 register (mpchsel0) . . . . . . . . . . . . . . . 2-57 2.4 channel indication logic (chi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58 2.4.1 chi configuration register (vmodr) . . . . . . . . . . . . . . . . . . . . . . . 2-58 2.4.2 chi control registers (vdatr0:vdatr3) . . . . . . . . . . . . . . . . . . . 2-59 2.5 fsc with delay (fscd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60 2.6 digital signal processor (dsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 2.6.1 dsp kernel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 2.6.2 dsp instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 2.7 dsp control unit (dcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 2.7.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 2.7.2 dsp address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 2.7.3 control of external memories / registers . . . . . . . . . . . . . . . . . . . . . 2-63 2.7.3.1 memory configuration register (memconfr) . . . . . . . . . . . . . . . 2-68 2.7.3.2 test configuration register (testconfr) . . . . . . . . . . . . . . . . . . 2-69 2.7.4 emulation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 2.7.5 interrupt handling and test support . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 2.7.6 run time statistics counter and register (statc and statr) . . . 2-71 2.7.7 program write protection register (passr) . . . . . . . . . . . . . . . . . . 2-73 2.7.8 serial (via jtag) emulation configuration register (jconf) . . . . . 2-73 2.7.9 boot support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 2.7.9.1 boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 2.7.9.2 emulation boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 2.7.9.3 boot procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 2.7.9.4 boot rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 2.7.9.5 m p boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76 2.7.9.6 mail box instructions format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77 2.7.9.7 write program memory command . . . . . . . . . . . . . . . . . . . . . . . . . 2-77 2.7.9.8 oak opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78 2.7.9.9 boot configuration register (bootconf) . . . . . . . . . . . . . . . . . . 2-79 2.7.9.10 the bootroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79 2.7.10 sine table rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87 2.8 pcm-dsp interface unit (pediu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88 2.8.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88 peb 20560 table of contents page semiconductor group i-3 1997-11-01 2.8.2 pediu internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93 2.8.2.1 pediu control register (ucr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93 2.8.2.2 pediu status register (usr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97 2.8.2.3 pediu input stream bypass enable register (uisbper) . . . . . . 2-101 2.8.2.4 pediu output stream bypass enable register (uosbper) . . . 2-103 2.8.2.5 pediu tri-state register (utsr) . . . . . . . . . . . . . . . . . . . . . . . . 2-104 2.8.2.6 pediu rom test address register (uprtar) and pediu rom test data register (uprtdr) . . . . . . . . . . . . . . . . 2-106 2.8.3 pediu synchronization and clock rates . . . . . . . . . . . . . . . . . . . . 2-107 2.8.3.1 pediu synchronization by fsc and dcl . . . . . . . . . . . . . . . . . . 2-107 2.8.3.2 restrictions on pediu clock rates . . . . . . . . . . . . . . . . . . . . . . . 2-108 2.8.4 pediu address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108 2.8.5 pediu data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-109 2.8.5.1 pediu serial data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-109 2.8.5.2 pediu parallel data processing . . . . . . . . . . . . . . . . . . . . . . . . . 2-109 2.8.5.3 the circular buffer address method . . . . . . . . . . . . . . . . . . . . . . 2-111 2.8.6 a-/ m -law conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-114 2.9 on-chip emulation (ocem) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115 2.10 mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115 2.10.1 m p mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115 2.10.2 oak mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-116 2.11 m p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-118 2.11.1 compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-118 2.11.2 memory and i/o organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-118 2.12 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-119 2.12.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-119 2.12.2 types of clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-120 2.12.2.1 input/output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-120 2.12.2.2 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-120 2.12.3 clocks generator registers description . . . . . . . . . . . . . . . . . . . . . 2-125 2.12.3.1 clocks select 0 register (ccsel0) . . . . . . . . . . . . . . . . . . . . . . . 2-125 2.12.3.2 clocks select 1 register (ccsel1) . . . . . . . . . . . . . . . . . . . . . . . 2-126 2.12.3.3 clocks select 2 register (ccsel2) . . . . . . . . . . . . . . . . . . . . . . . 2-128 2.13 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-129 2.13.1 mask (imask0, imask1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-129 2.13.2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-130 2.13.3 interrupt priority (ipar0, ipar1, ipar2) . . . . . . . . . . . . . . . . . . . . 2-130 2.13.4 interrupt cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132 2.13.4.1 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133 2.13.4.2 daisy chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-134 2.13.5 global interrupt status registers (igis0 and igis1) . . . . . . . . . . . 2-135 2.14 universal asynchronous receiver/transmitter (uart) . . . . . . . . . . 2-136 peb 20560 table of contents page semiconductor group i-4 1997-11-01 2.14.1 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-139 2.14.1.1 line control register (lcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-143 2.14.1.2 programmable baud rate generator (divisors) . . . . . . . . . . . . . . 2-144 2.14.1.3 line status register (lsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-145 2.14.1.4 fifo control register (fcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-148 2.14.1.5 interrupt identification register (iir) . . . . . . . . . . . . . . . . . . . . . . . 2-149 2.14.1.6 interrupt enable register (ier) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-151 2.14.1.7 modem control register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-151 2.14.1.8 modem status register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-153 2.14.1.9 scratchpad register (scr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-154 2.14.2 fifo interrupt mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-154 2.14.3 fifo polled mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-155 2.15 general purpose i/o port (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-156 2.15.1 i/o port support lines (mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-156 2.15.2 sacco-b0 support lines (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . 2-156 2.15.3 uart support lines (mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-156 2.15.4 configuration register (vcfgr) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-157 2.15.5 data register (vdatr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-157 2.15.6 version number register (vnr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-158 2.16 boundary scan support (jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-158 2.16.1 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-158 2.16.2 tap-controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-159 2.17 reset logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-160 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 elic0 and elic1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 interrupt structure and logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.2 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.3 epic ? -1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.3.1 pcm-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.3.2 configurable interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.3.3 switching functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.1.3.4 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.1.4 sacco-a/b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.1.4.1 data transmission in interrupt mode . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.1.4.2 data transmission in dma-mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.1.4.3 data reception in interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.1.4.4 data reception in dma-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.1.5 d-channel arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.1.5.1 sacco-a transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.1.5.2 sacco-a reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.1.6 initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 peb 20560 table of contents page semiconductor group i-5 1997-11-01 3.1.6.1 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.1.6.2 epic ? -1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.1.6.2.1 epic ? registers initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.1.6.2.2 control memory reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.1.6.2.3 initialization of pre-processed channels . . . . . . . . . . . . . . . . . . . 3-18 3.1.6.2.4 initialization of the upstream data memory (dm) tri-state field . 3-19 3.1.6.3 sacco-initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.1.6.4 initialization of d-channel arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.1.6.5 activation of the pcm- and cfi-interfaces . . . . . . . . . . . . . . . . . . . 3-22 3.1.6.6 initialization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.1.6.6.1 epic ? -1 initialization example . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.1.6.6.2 sacco-a initialization example . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.1.6.6.3 d-channel arbiter initialization example . . . . . . . . . . . . . . . . . . . 3-26 3.1.6.6.4 pcm- and cfi-interface activation example . . . . . . . . . . . . . . . . 3-27 3.1.6.6.5 sacco-b initialization example . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.2 sidec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 4 dsp core oak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2 architecture highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 architecture features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.2 buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.1 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.2.2 program buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.2.3 memory spaces and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.3.1 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.3.2 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.1 coff macro assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.2 linker/locator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.3 object format convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.4 ansi c-compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.5 simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.3.6 debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 5 description of registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 m p address space register overview . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 elic0 and elic1 registers description . . . . . . . . . . . . . . . . . . . . . . 5-22 5.1.1.1 interrupt top level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.1.1.1.1 interrupt status register (ista) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 peb 20560 table of contents page semiconductor group i-6 1997-11-01 5.1.1.1.2 mask register (mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.1.1.2 watchdog timer (in elic0 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.1.1.2.1 watchdog control register (wtc) . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.1.1.3 elic ? mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.1.1.4 epic ? -1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.1.1.4.1 pcm-mode register (pmod) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.1.1.4.2 bit number per pcm-frame (pbnr) . . . . . . . . . . . . . . . . . . . . . . 5-28 5.1.1.4.3 pcm-offset downstream register (pofd) . . . . . . . . . . . . . . . . . 5-28 5.1.1.4.4 pcm-offset upstream register (pofu) . . . . . . . . . . . . . . . . . . . 5-29 5.1.1.4.5 pcm-clock shift register; within the elic (pcsr) . . . . . . . . . . . 5-29 5.1.1.4.6 pcm-input comparison mismatch (picm) . . . . . . . . . . . . . . . . . . 5-30 5.1.1.4.7 configurable interface mode register 1 (cmd1) . . . . . . . . . . . . . 5-30 5.1.1.4.8 configurable interface mode register 2 (cmd2) . . . . . . . . . . . . . 5-33 5.1.1.4.9 configurable interface bit number register (cbnr) . . . . . . . . . . 5-34 5.1.1.4.10 configurable interface time-slot adjustment register (ctar) . . 5-35 5.1.1.4.11 configurable interface bit shift register (cbsr) . . . . . . . . . . . . . 5-35 5.1.1.4.12 configurable interface subchannel register (cscr) . . . . . . . . . 5-37 5.1.1.4.13 memory access control register (macr) . . . . . . . . . . . . . . . . . . 5-38 5.1.1.4.14 memory access address register (maar) . . . . . . . . . . . . . . . . . 5-42 5.1.1.4.15 memory access data register (madr) . . . . . . . . . . . . . . . . . . . . 5-43 5.1.1.4.16 synchronous transfer data register (stda) . . . . . . . . . . . . . . . 5-43 5.1.1.4.17 synchronous transfer data register b (stdb) . . . . . . . . . . . . . . 5-43 5.1.1.4.18 synchronous transfer receive address register a (sara) . . . . 5-44 5.1.1.4.19 synchronous transfer receive address register b (sarb) . . . . 5-44 5.1.1.4.20 synchronous transfer transmit address register a (saxa) . . . 5-45 5.1.1.4.21 synchronous transfer transmit address register b (saxb) . . . 5-45 5.1.1.4.22 synchronous transfer control register (stcr) . . . . . . . . . . . . . 5-46 5.1.1.4.23 mf-channel active indication register (mfair) . . . . . . . . . . . . . 5-47 5.1.1.4.24 mf-channel subscriber address register (mfsar) . . . . . . . . . . 5-47 5.1.1.4.25 monitor/feature control channel fifo (mffifo) . . . . . . . . . . . . 5-48 5.1.1.4.26 signaling fifo (cififo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48 5.1.1.4.27 timer register (timr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 5.1.1.4.28 status register epic ? -1 (star_e) . . . . . . . . . . . . . . . . . . . . . . . 5-49 5.1.1.4.29 command register epic ? -1 (cmdr_e) . . . . . . . . . . . . . . . . . . . 5-50 5.1.1.4.30 interrupt status register epic ? -1 (ista_e) . . . . . . . . . . . . . . . . 5-52 5.1.1.4.31 mask register epic ? -1 (mask_e) . . . . . . . . . . . . . . . . . . . . . . . 5-53 5.1.1.4.32 operation mode register (omdr) . . . . . . . . . . . . . . . . . . . . . . . . 5-54 5.1.1.4.33 version number status register (vnsr) . . . . . . . . . . . . . . . . . . . 5-56 5.1.1.5 sacco-a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56 5.1.1.5.1 receive fifo (rfifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56 5.1.1.5.2 transmit fifo (xfifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 5.1.1.5.3 interrupt status register (ista_a/b) . . . . . . . . . . . . . . . . . . . . . . 5-57 peb 20560 table of contents page semiconductor group i-7 1997-11-01 5.1.1.5.4 mask register (mask_a/b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 5.1.1.5.5 extended interrupt register (exir_a/b) . . . . . . . . . . . . . . . . . . . 5-58 5.1.1.5.6 command register (cmdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59 5.1.1.5.7 mode register (mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 5.1.1.5.8 channel configuration register 1 (ccr1) . . . . . . . . . . . . . . . . . . 5-61 5.1.1.5.9 channel configuration register 2 (ccr2) . . . . . . . . . . . . . . . . . . 5-62 5.1.1.5.10 receive length check register (rlcr) . . . . . . . . . . . . . . . . . . . 5-62 5.1.1.5.11 status register (star) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 5.1.1.5.12 receive status register (rsta) . . . . . . . . . . . . . . . . . . . . . . . . . 5-63 5.1.1.5.13 receive hdlc-control register (rhcr) . . . . . . . . . . . . . . . . . . . 5-65 5.1.1.5.14 transmit address byte 1 (xad1) . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 5.1.1.5.15 transmit address byte 2 (xad2) . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 5.1.1.5.16 receive address byte low register 1 (ral1) . . . . . . . . . . . . . . . 5-66 5.1.1.5.17 receive address byte low register 2 (ral2) . . . . . . . . . . . . . . . 5-66 5.1.1.5.18 receive address byte high register 1 (rah1) . . . . . . . . . . . . . . 5-67 5.1.1.5.19 receive address byte high register 2 (rah2) . . . . . . . . . . . . . . 5-67 5.1.1.5.20 receive byte count low (rbcl) . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 5.1.1.5.21 receive byte count high (rbch) . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5.1.1.5.22 version status register (vstr) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5.1.1.6 sacco-b register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5.1.1.6.1 receive fifo (rfifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5.1.1.6.2 transmit fifo (xfifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 5.1.1.6.3 interrupt status register (ista_a/b) . . . . . . . . . . . . . . . . . . . . . . 5-70 5.1.1.6.4 mask register (mask_a/b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71 5.1.1.6.5 extended interrupt register (exir_a/b) . . . . . . . . . . . . . . . . . . . 5-71 5.1.1.6.6 command register (cmdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72 5.1.1.6.7 mode register (mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-74 5.1.1.6.8 channel configuration register 1 (ccr1) . . . . . . . . . . . . . . . . . . 5-75 5.1.1.6.9 channel configuration register 2 (ccr2) . . . . . . . . . . . . . . . . . . 5-77 5.1.1.6.10 receive length check register (rlcr) . . . . . . . . . . . . . . . . . . . 5-78 5.1.1.6.11 status register (star) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78 5.1.1.6.12 receive status register (rsta) . . . . . . . . . . . . . . . . . . . . . . . . . 5-79 5.1.1.6.13 receive hdlc-control register (rhcr) . . . . . . . . . . . . . . . . . . . 5-81 5.1.1.6.14 transmit address byte 1 (xad1) . . . . . . . . . . . . . . . . . . . . . . . . . 5-81 5.1.1.6.15 transmit address byte 2 (xad2) . . . . . . . . . . . . . . . . . . . . . . . . . 5-82 5.1.1.6.16 receive address byte low register 1 (ral1) . . . . . . . . . . . . . . . 5-82 5.1.1.6.17 receive address byte low register 2 (ral2) . . . . . . . . . . . . . . . 5-83 5.1.1.6.18 receive address byte high register 1 (rah1) . . . . . . . . . . . . . . 5-83 5.1.1.6.19 receive address byte high register 2 (rah2) . . . . . . . . . . . . . . 5-83 5.1.1.6.20 receive byte count low (rbcl) . . . . . . . . . . . . . . . . . . . . . . . . . 5-84 5.1.1.6.21 receive byte count high (rbch) . . . . . . . . . . . . . . . . . . . . . . . . 5-84 5.1.1.6.22 transmit byte count low (xbcl) . . . . . . . . . . . . . . . . . . . . . . . . 5-84 peb 20560 table of contents page semiconductor group i-8 1997-11-01 5.1.1.6.23 transmit byte count high (xbch) . . . . . . . . . . . . . . . . . . . . . . . . 5-85 5.1.1.6.24 time-slot assignment register transmit (tsax) . . . . . . . . . . . . 5-85 5.1.1.6.25 time-slot assignment register receive (tsar) . . . . . . . . . . . . . 5-86 5.1.1.6.26 transmit channel capacity register (xccr) . . . . . . . . . . . . . . . 5-86 5.1.1.6.27 receive channel capacity register (rccr) . . . . . . . . . . . . . . . . 5-86 5.1.1.6.28 version status register (vstr) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87 5.1.1.7 d-channel arbiter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87 5.1.1.7.1 arbiter mode register (amo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-87 5.1.1.7.2 arbiter state register (astate) . . . . . . . . . . . . . . . . . . . . . . . . . 5-88 5.1.1.7.3 suspend counter value register (scv) . . . . . . . . . . . . . . . . . . . 5-88 5.1.1.7.4 d-channel enable register iom ? -port 0 (dce0) . . . . . . . . . . . . 5-89 5.1.1.7.5 d-channel enable register iom ? -port 1 (dce1) . . . . . . . . . . . . 5-89 5.1.1.7.6 d-channel enable register iom ? -port 2 (dce2) . . . . . . . . . . . . 5-89 5.1.1.7.7 d-channel enable register iom ? -port 3 (dce3) . . . . . . . . . . . . 5-89 5.1.1.7.8 transmit d-channel address register (xdc) . . . . . . . . . . . . . . . 5-90 5.1.1.7.9 broadcast group iom ? -port 0 (bcg0) . . . . . . . . . . . . . . . . . . . . . 5-90 5.1.1.7.10 broadcast group iom ? -port 1 (bcg1) . . . . . . . . . . . . . . . . . . . . . 5-90 5.1.1.7.11 broadcast group iom ? -port 2 (bcg2) . . . . . . . . . . . . . . . . . . . . . 5-90 5.1.1.7.12 broadcast group iom ? -port 3 (bcg3) . . . . . . . . . . . . . . . . . . . . . 5-91 5.1.2 sidec register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91 5.1.2.1 receive fifo (rfifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91 5.1.2.2 transmit fifo (xfifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91 5.1.2.3 interrupt status register (ista_a/b) . . . . . . . . . . . . . . . . . . . . . . . 5-92 5.1.2.4 mask register (mask_a/b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-92 5.1.2.5 extended interrupt register (exir_a/b) . . . . . . . . . . . . . . . . . . . . 5-93 5.1.2.6 command register (cmdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94 5.1.2.7 mode register (mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96 5.1.2.8 channel configuration register 1 (ccr1) . . . . . . . . . . . . . . . . . . . 5-97 5.1.2.9 channel configuration register 2 (ccr2) . . . . . . . . . . . . . . . . . . . 5-98 5.1.2.10 receive length check register (rlcr) . . . . . . . . . . . . . . . . . . . . 5-99 5.1.2.11 status register (star) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99 5.1.2.12 receive status register (rsta) . . . . . . . . . . . . . . . . . . . . . . . . . 5-100 5.1.2.13 receive hdlc-control register (rhcr) . . . . . . . . . . . . . . . . . . . 5-102 5.1.2.14 transmit address byte 1 (xad1) . . . . . . . . . . . . . . . . . . . . . . . . . 5-102 5.1.2.15 transmit address byte 2 (xad2) . . . . . . . . . . . . . . . . . . . . . . . . . 5-103 5.1.2.16 receive address byte low register 1 (ral1) . . . . . . . . . . . . . . . 5-103 5.1.2.17 receive address byte low register 2 (ral2) . . . . . . . . . . . . . . . 5-104 5.1.2.18 receive address byte high register 1 (rah1) . . . . . . . . . . . . . . 5-104 5.1.2.19 receive address byte high register 2 (rah2) . . . . . . . . . . . . . . 5-104 5.1.2.20 receive byte count low (rbcl) . . . . . . . . . . . . . . . . . . . . . . . . . 5-105 5.1.2.21 receive byte count high (rbch) . . . . . . . . . . . . . . . . . . . . . . . . 5-105 5.1.2.22 time-slot assignment register transmit (tsax) . . . . . . . . . . . . 5-105 peb 20560 table of contents page semiconductor group i-9 1997-11-01 5.1.2.23 time-slot assignment register receive (tsar) . . . . . . . . . . . . . 5-106 5.1.2.24 transmit channel capacity register (xccr) . . . . . . . . . . . . . . . 5-106 5.1.2.25 receive channel capacity register (rccr) . . . . . . . . . . . . . . . . 5-106 5.1.2.26 version status register (vstr) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107 6 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 doc in a small pbx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 small pbx with 2.048 mbit/s data rate . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.2 small pbx with 4.096 mbit/s data rate . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 doc on line card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2.1 line card with 2.048 and 4.096 mbit/s data rates . . . . . . . . . . . . . . 6-4 6.2.2 line card with 4.096 and 8.192 mbit/s data rates . . . . . . . . . . . . . . 6-5 6.3 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.3.1 pbx with one doc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.3.2 pbx with multiple docs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.4 signaling with sidec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.5 local network controller (sacco-b1 as lnc) . . . . . . . . . . . . . . . . . . 6-9 6.6 uart applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.7 iom ? -2 channel indication signal (chi) . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.8 use of fscd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.9 watch-dog activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.10 tone and voice processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.11 dsp frequency recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.4 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.5 strap pins pull-up resistors specification . . . . . . . . . . . . . . . . . . . . . . 7-3 7.6 40 mhz external crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.7 general recommendations and prohibitions . . . . . . . . . . . . . . . . . . . . 7-4 7.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.9 microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.9.1 pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.9.2 iom ? -2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7.9.3 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 7.9.4 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 7.9.5 boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 7.9.6 dsp external memory interface timing . . . . . . . . . . . . . . . . . . . . . . 7-35 7.9.7 clocks signals timing (additional to the iom ? -2 and pcm clocks) . 7-45 peb 20560 table of contents page semiconductor group i-10 1997-11-01 8 ordering information and mechanical data . . . . . . . . . . . . . . . . . 8-1 8.1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 9 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1.1 signals / channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1.2 monitor and c/i handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.1.3 iom ? -2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 working sheets for multiplexers programming . . . . . . . . . . . . . . . . . . . 9-4 9.3 working sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3.1 register summary for epic ? initialization . . . . . . . . . . . . . . . . . . . . . 9-5 9.3.2 switching of pcm time-slots to the cfi interface (data downstream) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.3 switching of cfi time-slots to the pcm interface (data upstream) 9-10 9.3.4 preparing epics c/i channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.3.5 receiving and transmitting iom ? -2 c/i-codes . . . . . . . . . . . . . . . . 9-12 9.3.6 doc port and signaling multiplexers . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.3.7 doc clocking multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.4 development tools and software support . . . . . . . . . . . . . . . . . . . . . 9-15 9.4.1 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.4.2 macro assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.4.3 linker/locator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.4.4 c compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.4.5 object format converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.4.6 simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.5 oak development / evaluation board . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.6 doc configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 10 acronym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 iom ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4 m c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of siemens ag. semiconductor group i-11 1997-11-01 peb 20560 list of figures page figure 1-1 functional blocks of a pbx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 figure 1-2 application example pbx for 32 subscribers with 4 trunk lines using one doc . . . . . . . . . 1-2 figure 1-3 principle block diagram of the doc . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 figure 1-4 doc logic symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 figure 1-5 doc pin configuration (p-mqfp-160 package) . . . . . . . . . . . . . . . . . . 1-8 figure 1-6 functional block diagram and system integration . . . . . . . . . . . . . . . 1-25 figure 1-7 example for a pbx with one doc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 figure 2-1 epic ? -1 memory structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 figure 2-2 timing diagram for dma-transfers (fast) transmit (n < 32, remainder of a long message or n = k 32) . . . . . . . . . . . . . . . . . . . . . 2-7 figure 2-3 timing diagram for dma-transfers (slow) transmit (n < 32, remainder of a long message or n = k 32) . . . . . . . . . . . . . . . . . . . . . 2-8 figure 2-4 timing diagram for dma-transfer (fast) receive (n = k 32). . . . . . . . 2-8 figure 2-5 timing diagram for dma-transfers (slow) receive (n = k 32) . . . . . . 2-8 figure 2-6 timing diagram for dma-transfers (slow or fast) receive (n = 4, 8 or 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 figure 2-7 dma-transfers with pulsed dack (read or write) . . . . . . . . . . . . . . . . . 2-9 figure 2-8 frame storage in rfifo (single frame / multiple frames) . . . . . . . . . . 2-10 figure 2-9 xfifo loading, continuous frame transmission disabled (cft = 0) 2-11 figure 2-10 xfifo loading, continuous frame transmission enabled (cft = 1) 2-12 figure 2-11 support of the hdlc protocol by the sacco . . . . . . . . . . . . . . . . . . . 2-13 figure 2-12 polling of up to 64 bytes direct data . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 figure 2-13 polling more than 64 bytes of direct data (e.g. 96 bytes) . . . . . . . . . . 2-19 figure 2-14 re-transmission of a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 figure 2-15 re-transmission of a frame with auto-repeat function . . . . . . . . . . 2-21 figure 2-16 polling of prepared data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 figure 2-17 receive data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 figure 2-18 location of time-slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 figure 2-19 d-channel arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 figure 2-20 arbiter state machine (asm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 figure 2-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 figure 2-22 sidec block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 figure 2-23 sidec signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 figure 2-24 principle block diagram of iom and pcm multiplexers; mode 0-0-0-0-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 figure 2-25 modes of hdlc connection to iom ? -2 interfaces within the signaling mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 figure 2-26 iom ? ports multiplexer in mode 1 and elic ? -1-ports multiplexer in mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 figure 2-27 pcm-ports multiplexer in mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 figure 2-28 sacco-b0 multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 semiconductor group i-12 1997-11-01 peb 20560 list of figures page figure 2-29 quat-s with sacco-b for single-channel lt-t application. . . . . . . 2-49 figure 2-30 sacco-b1 multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 figure 2-31 pediu connection to the elics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52 figure 2-32 chi signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58 figure 2-33 fscd behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60 figure 2-34 external data/program read access . . . . . . . . . . . . . . . . . . . . . . . . . 2-64 figure 2-35 external data write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65 figure 2-36 external program write access due to movd . . . . . . . . . . . . . . . . . . 2-66 figure 2-37 external boot rom read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67 figure 2-38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71 figure 2-39 example: flow of b-channels between elic1 and pediu . . . . . . . . . 2-89 figure 2-40 accesses to the pediu ram (circular buffer) at two consecutive frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90 figure 2-41 block diagram of the pcm-dsp interface unit (pediu) . . . . . . . . . . . 2-92 figure 2-42 block structure of circular buffer (pediu ram) in different pediu work modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-96 figure 2-43 connection between cb bit and accesses to the circular buffer blocks in pediu work mode 0, 1 or 2 . . . . . . . . . . . . . . . . . . . . 2-99 figure 2-44 the connection between cb bit and accesses to the circular buffer blocks in pediu work mode 3 or 4 . . . . . . . . . . . . . . . . . . . . . 2-100 figure 2-45 doc clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-119 figure 2-46 pfs signal selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121 figure 2-47 pdc generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-122 figure 2-48 priority unit - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-131 figure 2-49 interrupt cascading (slave mode) in siemens/intel bus mode . . . . . 2-133 figure 2-50 interrupt cascading (daisy chaining) in siemens/intel bus mode . . 2-134 figure 2-51 uart block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-138 figure 3-1 elic ? interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 figure 3-2 switching paths inside the epic ? -1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 figure 3-3 pre-processed channel codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 figure 3-4 interrupt driven transmission sequence (flow diagram) . . . . . . . . . . 3-11 figure 3-5 interrupt driven transmission sequence example . . . . . . . . . . . . . . . 3-12 figure 3-6 dma driven transmission example . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 figure 3-7 interrupt driven reception example . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 figure 3-8 dma-driven reception example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 figure 3-9 doc/elic ? interfaces for initialization example . . . . . . . . . . . . . . . . . 3-23 figure 4-1 program memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 figure 4-2 data memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 figure 5-1 timing relation between internal and external clock . . . . . . . . . . . . . 5-25 figure 5-2 position of the fsc-signal for fc-modes 3 and 6 . . . . . . . . . . . . . . . . 5-33 figure 5-3 position of the fsc-signal for fc-mode 6. . . . . . . . . . . . . . . . . . . . . . 5-33 semiconductor group i-13 1997-11-01 peb 20560 list of figures page figure 5-4 internal fsc shift to enable a synchronization with the rising edge of dcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 figure 5-5 use of cts signal in sidec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99 figure 6-1 doc in a small pbx with 2.048 mbit/s data rate . . . . . . . . . . . . . . . . . 6-2 figure 6-2 doc in a small pbx with 4.096 mbit/s data rate . . . . . . . . . . . . . . . . . 6-3 figure 6-3 doc on line card with 2.048 and 4.096 mbit/s data rates . . . . . . . . . 6-4 figure 6-4 doc on line card with 4.096 and 8.192 mbit/s data rates . . . . . . . . . 6-5 figure 6-5 clock generation in a pbx with one doc . . . . . . . . . . . . . . . . . . . . . . . 6-6 figure 6-6 clock synchronization in a pbx with multiple docs . . . . . . . . . . . . . . . 6-7 figure 6-7 quat-s in lt-t mode with sidec for four-channel trunk applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 figure 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 figure 7-2 i/o-wave form for ac-test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 figure 7-3 address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 figure 7-4 data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 figure 7-5 siemens/intel interrupt timing (slave mode) . . . . . . . . . . . . . . . . . . . . . 7-8 figure 7-6 siemens/intel interrupt timing (daisy chaining). . . . . . . . . . . . . . . . . . . 7-9 figure 7-7 motorola interrupt timing (slave mode). . . . . . . . . . . . . . . . . . . . . . . . 7-11 figure 7-8 motorola interrupt timing (daisy chaining) . . . . . . . . . . . . . . . . . . . . . 7-12 figure 7-9 interrupt inactivation from wr, rd. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 figure 7-10 pdc and pfs timing in master mode (pdc & pfs are outputs) . . . . 7-15 figure 7-11 pcm-interface timing in master mode. . . . . . . . . . . . . . . . . . . . . . . . . 7-17 figure 7-12 pcm-interface timing in slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 figure 7-13 iom ? -2 interface clocks timing when fsc and dcl are driven by elic0 and the doc is in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 figure 7-14 iom ? -2 interface clocks timing when fsc and dcl are driven directly by pdc4/8 and pfs, and the doc is in slave mode . . . . . . . 7-22 figure 7-15 iom ? -2 interface clocks timing when fsc and dcl are driven directly by pdc4/8 and pfs, and the doc is in master mode (pdc and pfs are generated by internal clocks generator) . . . . . . . . 7-24 figure 7-16 iom ? -2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 figure 7-17 fscd timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 figure 7-18 channel indication (chi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 figure 7-19 drdy timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 figure 7-20 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 figure 7-21 serial interface strobe timing (clock mode 1) . . . . . . . . . . . . . . . . . . . 7-32 figure 7-22 serial interface synchronization timing (clock mode 2) . . . . . . . . . . . 7-33 figure 7-23 dreset and resin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 figure 7-24 boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35 figure 7-25 program read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 figure 7-26 external ram data read access timing diagram . . . . . . . . . . . . . . . 7-39 figure 7-27 emulation mail-box read access timing diagram . . . . . . . . . . . . . . . 7-40 semiconductor group i-14 1997-11-01 peb 20560 list of figures page figure 7-28 boot rom read access timing diagram . . . . . . . . . . . . . . . . . . . . . . 7-41 figure 7-29 external data write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43 figure 7-30 emulation mail-box write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44 figure 7-31 external program write access due to movd . . . . . . . . . . . . . . . . . . 7-45 figure 7-32 clk61 (input) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 figure 7-33 clk16 (input) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 figure 7-34 refclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47 figure 7-35 xclk (input) timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47 figure 7-36 clk30 (output) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 figure 7-37 clk15 (output) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 figure 7-38 clk7 (output) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49 figure 8-1 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 figure 9-1 iom ? -2 interface with 4-bit c/i channel. . . . . . . . . . . . . . . . . . . . . . . . . 9-1 figure 9-2 iom ? -2 interface timing with single data rate dcl . . . . . . . . . . . . . . 9-2 figure 9-3 timing of the iom ? -2 interface with double data rate dcl . . . . . . . . . 9-3 figure 9-4 a epic ? initialization register summary (working sheet) . . . . . . . . . . . . 9-5 figure 9-4 b switching of pcm time-slots to the cfi interface (working sheet) . . . . 9-9 figure 9-4 c switching of cfi time-slots to the pcm interface (working sheet) . . . 9-10 figure 9-4 d preparing epic ? s c/i channels (working sheet). . . . . . . . . . . . . . . . . 9-11 figure 9-5 receiving and transmitting iom ? -2 c/i-codes (working sheet) . . . . . 9-12 figure 9-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 figure 9-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 figure 9-8 doc evaluation board - block diagram . . . . . . . . . . . . . . . . . . . . . . . 9-16 figure 9-9 doc evaluation system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 figure 9-10 example for sidecs and saccos assignment . . . . . . . . . . . . . . . . . 9-18 figure 9-11 example for selection of elic clocks . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 semiconductor group i-15 1997-11-01 peb 20560 list of tables page table 1-1 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 table 1-2 pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 table 1-3 communication and signaling interfaces. . . . . . . . . . . . . . . . . . . . . . 1-13 table 1-4 dsp external memory interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 table 1-5 clock signals (additional to the iom ? -2, pcm and scc clocks) . . . . 1-18 table 1-6 m p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 table 1-7 input / output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 table 1-8 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 table 1-9 test and emulation interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 table 2-1 watchdog timer programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 table 2-2 reset activities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 table 2-3 behavior of the reset logic in the case of voltage drop . . . . . . . . . . 2-3 table 2-4 address recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 table 2-5 auto-mode data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 table 2-6 hdlc-control field in auto-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 table 2-7 auto-mode command byte interpretation . . . . . . . . . . . . . . . . . . . . . 2-16 table 2-8 auto-mode response generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 table 2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 table 2-10 control channel implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 table 2-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 table 2-12 control channel delay examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 table 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 table 2-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 table 2-15 dsp program address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 table 2-16 dsp data address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 table 2-17 interrupt map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 table 2-18 boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74 table 2-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 table 2-20 eprom/rom data structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76 table 2-21 work modes specifications of the pediu . . . . . . . . . . . . . . . . . . . . . 2-94 table 2-22 address spaces of circular buffer blocks as a function of the pediu work mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95 table 2-23 specification of the time-slot quadruplet controlled by each bit in uisb-per, in the different work modes of the pediu . . . . . . . . . 2-101 table 2-24 specification of the time-slot quadruplet that controlled by each bit in uosbper, in the different work modes of the pediu . . 2-104 table 2-25 specification of the time-slot quadruplet controlled by each bit in uosb-per, in the different work modes of the pediu . . . . . . . . 2-105 table 2-26 pediu registers addresses in the dsp address space. . . . . . . . . 2-108 table 2-27 register contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-117 table 2-28 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-130 table 2-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133 semiconductor group i-16 1997-11-01 peb 20560 list of tables page table 2-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-135 table 2-31 summary of registers 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-139 table 2-32 summary of registers 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-140 table 2-33 register reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-141 table 2-34 uart registers and addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142 table 2-35 baud rates using 61.44 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . 2-145 table 2-36 iir register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-149 table 2-37 boundary scan cell types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-158 table 2-38 instruction code of 4 bit tap controller . . . . . . . . . . . . . . . . . . . . . . 2-159 table 2-39 data path of 4 bit tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-159 table 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 table 3-2 pre-processed channel options at the cfi . . . . . . . . . . . . . . . . . . . . . 3-18 table 3-3 mode dependent register set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 table 3-4 feature dependent register set-up . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 table 3-5 mode dependent register set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 table 3-6 feature dependent register set-up . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 table 5-1 elic0 sacco-a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 table 5-2 elic0 sacco-b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 table 5-3 elic0-epic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 table 5-4 elic0-mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 table 5-5 elic0-watch-dog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 table 5-6 elic0-interrupt top level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 table 5-7 elic0-arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 table 5-8 elic1 sacco-a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 table 5-9 elic1 sacco-b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 table 5-10 elic1-epic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 table 5-11 elic1-mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-12 elic1-interrupt top level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-13 elic1-arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-14 sidec0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 table 5-15 sidec1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 table 5-16 sidec2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 table 5-17 sidec3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 table 5-18 icu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 table 5-19 gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 table 5-20 chi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 table 5-21 oak mail box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 table 5-22 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 table 5-23 iom/pcm mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 table 5-24 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 table 5-25 pediu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 table 5-26 dcu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 semiconductor group i-17 1997-11-01 peb 20560 list of tables page table 5-27 oak mail box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 table 5-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 table 5-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 table 5-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 table 5-31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 table 5-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 table 5-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 table 5-34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 table 5-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 table 5-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 table 5-37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 table 5-38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 table 5-39 downstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 table 5-40 upstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 table 5-41 time-slot encoding for data memory accesses . . . . . . . . . . . . . . . . 5-42 table 5-42 time-slot encoding for control memory accesses . . . . . . . . . . . . . . 5-42 table 5-43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 table 5-44 summary of mf-channel commands . . . . . . . . . . . . . . . . . . . . . . . . 5-51 table 5-45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 table 5-46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69 table 5-47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98 table 6-1 an example for required dsp performance in a comfort pbx with 30 subscribers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 table 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 table 7-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 table 7-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 table 7-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 table 7-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 table 7-6 bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 table 7-7 siemens/intel interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 table 7-8 motorola interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 table 7-9 interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 table 7-10 pdc and pfs timing in master mode . . . . . . . . . . . . . . . . . . . . . . . . 7-13 table 7-11 pcm-interface timing in master mode. . . . . . . . . . . . . . . . . . . . . . . . 7-15 table 7-12 pcm interface timing in slave mode. . . . . . . . . . . . . . . . . . . . . . . . . 7-18 table 7-13 iom ? -2 interface clocks timing when fsc and dcl are driven by elic0 and the doc is in slave mode . . . . . . . . . . . . . . . . . . . . . . . 7-20 table 7-14 iom ? -2 interface clocks timing when fsc and dcl are driven directly by pdc4/8 and pfs, and the doc is in slave mode . . . . . . . 7-22 table 7-15 iom ? -2 interface clocks timing when fsc and dcl are driven directly by pdc4/8 and pfs, and the doc is in master mode (pdc and pfs are generated by internal clocks generator) . . . . . . . . 7-23 semiconductor group i-18 1997-11-01 peb 20560 list of tables page table 7-16 iom ? -2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 table 7-17 fscd (delayed fsc) timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 table 7-18 channel indication (chi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 table 7-19 drdy timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 table 7-20 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 table 7-21 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 table 7-22 boundary scan timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 table 7-23 program read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35 table 7-24 external data read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 table 7-25 external program/data write access. . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 table 7-26 clk61 (input) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45 table 7-27 clk16 (input) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 table 7-28 refclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 table 7-29 xclk (input) timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47 table 7-30 clk30 (output) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 table 7-31 clk15 (output) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 table 7-32 clk7 (output) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49 table 9-1 timing characteristics of the iom ? -2 . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 table 9-2 timing characteristics of the iom ? -2 . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 peb 20560 overview semiconductor group 1-1 1997-11-01 1 overview a small pbx and a line card consist of the following main functional blocks: a switching matrix, multiple layer-1 transceivers for t/r (a/b), s/t, u p and u k interfaces, iom-2 interface controller, signaling controllers, a dsp for tone and voice management, a microprocessor, memory, clock generator, power supply and transformers. figure 1-1 shows main functional blocks of a pbx. . figure 1-1 functional blocks of a pbx itb10067 codec t/r slic t/r layer-1 u p u p layer-1 s/t s/t k u layer-1 u k signaling clock generator controllers r iom -2 controller of layer-1 ics and switch pcm highways manage. voice and tone hdlc hdlc signaling controller local-network m p interface memory power uart supply m p v.24 peb 20560 overview semiconductor group 1-2 1997-11-01 the new siemens generation of highly integrated isdn circuits enables design engineers to decrease board size and thus pbx size and its production costs. figure 1-2 shows an example of a pbx for 16 isdn and 16 analog subscribers with 4 trunk lines realized with a few highly integrated chips of the new siemens family of pbx and line card ics: doc, sicofi-4, octat-p and quat-s. figure 1-2 application example pbx for 32 subscribers with 4 trunk lines using one doc doc , dsp oriented pbx controller, peb 20560, the doc integrates many different functional blocks on a single chip for building small pbxs or pbx line cards: two elics, enhanced line card controller (peb 20550), one sidec, 4-channel signaling controller its10068 peb 2465 slic t/r u p s t r iom -2 doc peb 20560 pcm highways memory data and program signaling m p interface memory power supply m p slic slic slic sicofi r -4 v.24 up to 56 kw dsp octat r -p peb 2096 quat peb 2084 -s r quat peb 2084 -s r 0 15 0 7 0 7 0 3 office central peb 20560 overview semiconductor group 1-3 1997-11-01 (lap-d), multiple iom-2 and pcm interfaces, one up-to 40 mips dsp with on-chip emulation and a mailbox, one pcm-dsp interface for fast dsp access, one uart, interrupt controller, the doc is a cmos device offered in a p-mqfp-160 package. quat ? -s , quadruple transceiver for s/t interfaces, peb 2084, implements 4 four-wire s/t interfaces to link voice/data digital terminals to pbx subscriber lines and pbx trunk lines to the public isdn. it can handle up to four s/t interfaces simultaneously in accordance with ccitt i.430, etsi 300.012, and ansi t1.605 standards. the quat-s is a cmos device offered in a p-mqfp-44 package. octat ? -p , octal transceiver for u pn interfaces, peb 2096, implements the two-wire u pn interface used to link voice/data digital terminals to pbx subscriber lines. the octat-p is an optimized device for lt applications and can handle up to eight u pn interfaces simultaneously. it handles the u pn interfaces in accordance with the u p0 interface specification except for the reduced loop length. the octat-p is a cmos device offered in a p-mqfp-44 package. sicofi ? -4, programmable signaling and codec filter with 4 channels, peb 2465, implements 4 t/r (a/b) interfaces to link analog voice terminals to pbx subscriber lines and analog pbx trunk lines to public switches. an integrated digital signal processor handles all the algorithms necessary e.g. transhybrid-loss adaption, gain, frequency response, impedance matching. the iom-2 interface handles digital voice transmission, sicofi-4 feature control and transparent access to the sicofi-4 command and indication pins. to program the filters, precalculated sets of coefficients are downloaded from the system to the on-chip coefficient ram. thus it is possible to use the same line card in different countries. the sicofi-4 is a cmos device offered in p-mqfp-64 package. isdn-oriented modular interface (iom ? -2) the group of four, alcatel, siemens, plessey and italtel systems houses, originally defined a general circuit interface (gci) with the aim of specifying a comprehensive interface which would allow various telecommunication devices to communicate in an efficient manner. the iom-2 interface is a four-wire interface. it became a standard interface for interchip communication in isdn applications. all above ics are compatible and operate from a single 5 v power supply (incl. sicofi-4). peb 20560 overview semiconductor group 1-4 1997-11-01 dsp oriented pbx controller (doc) the doc is comprising all necessary functional blocks like switching, signaling, dtmf/tone handling and conferencing on a single chip. the transceivers (layer 1 ics) are not integrated. . figure 1-3 principle block diagram of the doc itb10069 controller of layer-1 ics: handlers c/i and monitor switch or 96 x 256 time-slots 192 x 128 time-slots pcm interface controllers 6 x hdlc 2 hdlc controllers and d-channel arbiter dsp internal memory for tone, voice and data dsp processing clock generator jtag uart interrupt controller m p external dsp memory for program and data pcm highways r iom -2 interfaces p interface m m p-mail box p-mqfp-160-1 semiconductor group 1-5 1997-11-01 dsp oriented pbx controller doc peb 20560 version 2.1 cmos type ordering code package peb 20560 v2.1 q67231-h1007 p-mqfp-160-1 1.1 doc features the doc provides all necessary features for building pbx (privat branch exchange) systems and line cards. ? in the pbx mode ( figure 2-1 ), the doc provides: C 6 fully usable iom-2 (gci) interfaces and thus it can control up to 48 isdn or 96 analog subscribers. C 4 pcm highways with 128 time-slots in total. ? in the line card mode ( figure 2-3 ), the doc provides: C 2 fully usable iom-2 interfaces with 16 iom-2 subframes (2 8) and C 2 limited iom-2 interfaces, as two dsp ports are connected, and thus it can control 16 to 24 isdn (or 32 to 48 analogue) subscribers. C 4 pcm highways with 256 time-slots in total. ? signaling via 8 assignable hdlc controllers, each with a 64-byte data fifo for transmit and for receive direction. C 2 hdlc controllers (sacco-a) assignable to two of up to 48 isdn subscribers at a time via two different d-channel arbiters C 4 hdlc controllers (sidec) assignable to any d-/b-channel in data upstream or data downstream direction on four iom-2 interfaces. C 2 hdlc controllers (sacco-b) assignable to any time-slot in data upstream or data downstream direction of the four iom-2 interfaces or the pcm highways. optionally, both controllers can be used as stand alone hdlc controllers with up to 8.192 mbit/s transfer rate. they support dma operation. ? on-chip user programmable 16-bit digital signal processor, siemens oak, (with 20, 30 or up to 40 mips) with access to 64 time-slots (via one or two internal iom-2 interfaces) for dtmf/tone generation and recognition, conferencing, music-on-hold, modem emulation, etc. C 1 k 16-bit on-chip data memory (x) C 512 16-bit on-chip data memory (y) peb 20560 overview semiconductor group 1-6 1997-11-01 C dsp proprietary interface to an external memory: * program memory up to 56 k 16-bit * data memory up to 32 k 16-bit C on-chip program rom (boot) ~ 0.5 k 16-bit ? a-/ m -law coding and decoding by hardware (on the fly) ? firmware for dsp work load measurement (within every 125 m s frame) ? protection against write into program memory using password ? m p-dsp communication via two mail-boxes ? on-chip emulation (ocem) for dsp program debugging ? 8-bit m p interface compatible with siemens/intel bus schemes ? programmable clock generator with built-in logic for master and slave configurations ? watch-dog timer ? reset logic ? uart for v.24 interface ? multifunctional input/output port configurable as a general i/o port, dma lines for sacco-b0 or as additional uart lines for modem connection ? integrated interrupt controller with vector generation and support for doc cascading ? interrupt vector handling compatible with siemens/intel/motorola bus schemes ? up to 4 external interrupt inputs (via the general i/o port) ? jtag interface for on board tests ? interface for hw and sw dsp evaluation (debugging) ? advanced cmos 0.5 m m technology ? 3.3-v and 5-v power supply in 5-v environment 3.3-v power supply in 3.3-v environment ? ttl driving capability, ttl and cmos compatible inputs ? p-mqfp-160 package peb 20560 overview semiconductor group 1-7 1997-11-01 1.2 logic symbol figure 1-4 doc logic symbol (160 pins are used) itl10071 doc peb 20560 33 16 11 37 18 10 r iom -2 interfaces (incl. dsp interfaces) clock signals power supply pcm interfaces communication signaling and interfaces memory to external dsp interface 20 11 4 emulation test and interfaces i/o port interface m p peb 20560 overview semiconductor group 1-8 1997-11-01 1.3 pin configuration (top view) figure 1-5 doc pin configuration (p-mqfp-160 package) cab13 doc peb 20560 cab12 80 77 74 71 68 65 62 59 56 53 50 47 44 resin 41 120 117 114 111 108 105 102 99 96 93 90 87 84 81 121 124 127 130 133 136 139 142 145 148 151 154 157 40 37 34 31 28 25 22 19 16 13 10 7 4 160 1 itp10070 cab14 drdy cab15 refclk ss v v dd dd v v ss ss v xclk dd v clk7 cdb0/boot clk15 cdb1/dbg clk30 cdb2/rom v vcxo cdb3 clk16 ss v clk40-xo dd v clk40-xi cdb4/urst clk61 cdb5 v dd cdb6 v ss cdb7 ie1 ss v ie0 dd v iack cdb8 ireq cdb9 a9 cdb10 a8 cdb11 ad7 ss v ad6 dd v ad5 cdb12/seibdis ad4 cdb13 ad3 cdb14 ad2 cdb15 v dd ss v v ss dd v ad1 fscd ad0 cdrp rd cdpw wr cmbr cs cmbw rxd0 ss v rxd1 dd v rxd2 cbr rxd3 cts txd0 v dd rts v ss rxdu cab11 du7/dackb1 cab10 dd7/drqrb1 cab9 du6/cxdb1 cab8 dd6/drqtb1 v dd du5/hfsb1 v ss dd5/tsbc1 cab7 du4/rxdb1 cab6 dd4/txdb1 cab5 du3 cab4 dd3 du2 v dd dd2 v ss v ss cab3 cab2 du1 cab1 dd1 cab0 du0 ale dd0 abort dcl v dd fsc v ss pdc8 stop pdc4 dtclk pdc2 frq1 pfs frq0 cxdb0 tdo tscb0 tdi txdb0 tms rxdb0 jtclk v ss chi v dd oak_test tsc3 iop3/port3/hfsb0/dcd tsc2 iop2/port2/dackb0/ri tsc1 iop1/port1/drqrb0/dtr tsc0 iop0/port0/drqtb0/dsr txd3 sync txd2 dreset txd1 ddp v dd v txdu peb 20560 overview semiconductor group 1-9 1997-11-01 1.4 pin description table 1-1 iom ? -2 interface pin no. symbol in (i) out (o) during reset function 23 fsc i/o i f rame s ynchronization c lock (8 khz) 22 dcl i/o i d ata cl ock: single or double data rate. 21 dd0 o(od) high impedance d ata d ownstream iom-2 interface 0 20 du0 i i d ata u pstream iom-2 interface 0 19 dd1 o(od) high impedance d ata d ownstream iom-2 interface 1 18 du1 i i d ata u pstream iom-2 interface 1 15 dd2 o(od) high impedance d ata d ownstream iom-2 interface 2 14 du2 i i d ata u pstream iom-2 interface 2 13 dd3 o(od) high impedance d ata d ownstream iom-2 interface 3 12 du3 i i d ata u pstream iom-2 interface 3 11 dd4/ txdb1 o(od) o high impedance (from elic1) d ata d ownstream iom-2 iom-2 interface 4 / t ransmit serial d ata sacco channel b1 . data output line of the corresponding hdlc-transmit channel. data is sampled on the bit ccr1:ods the pins have push pull or open drain characteristic. when transmission is disabled (tsc = 1) or when bit ccr2:txde is reset the pin is in the state high impedance. 10 du4/ rxdb1 i i i d ata u pstream iom-2 interface 4 / r eceive serial d ata sacco channel b1 . the serial data received on this line is forwarded into the corresponding hdlc-receive channel. data is sampled on the C falling edge of hdc (ccr2:rds = 0) or C rising edge of hdc (ccr2:rds = 1). peb 20560 overview semiconductor group 1-10 1997-11-01 9 dd5/ tscb1 o(od) o high impedance (from elic1). d ata d ownstream iom-2 interface 5 / t ri- s tate c ontrol sacco channel b1 , active low. supplies a control signal for an external driver. when low the corresponding txd-outputs are valid. the detailed functionality is defined programming the sacco-registers ccr2:soc1,soc0. 8 du5/ hfsb1 i i i d ata u pstream iom-2 interface 5 / h dlc-interface f rame s ynchronization sacco channel b1 frame synchronization pulse in clock mode 2, data strobe in clock mode 1. 7 dd6/ drqtb1 o(od) o high impedance (from elic1) d ata d ownstream iom-2 interface 6 / d ma- r e q uest t ransmitter sacco channel b1 the transmitter of hdlc-channel sacco requests a dma-data transfer by activating this line. the drqt-pin remains high as long as the transmit fifo requires data transfers. the number of data bytes to be transferred from system memory to the fifo must be written first into the xbch, xbcl registers (byte count registers). 6 du6/ cxdb1 i i i d ata u pstream iom-2 interface 6 / c ollision d ata sacco channel b1 in a bus configuration, the external serial bus must be connected to the respective cxd pin for collision detection. in point-to-point con?gurations the pin provides a clear to send function. when 0/1 the transmit channel is enabled/disabled. if this function is not needed the cxdb1 input line has to be tied to v ss . table 1-1 iom ? -2 interface (contd) pin no. symbol in (i) out (o) during reset function peb 20560 overview semiconductor group 1-11 1997-11-01 note: du 7 0 pins can be used only as inputs and not as i/o pins. dd 7 0 pins can be used only as outputs and not as i/o pins. the sld mode, of the elics, within the doc, is not valid. if dcl is programmed to be input, fsc will also be an input. test0 and test1 pins must be connected to 0 when not used. 5 dd7/ drqrb1 o(od) o high impedance (from elic1) d ata d ownstream iom-2 interface 7 / d ma- r e q uest r eceiver channel b1 the receiver of sacco channel requests a dma-data transfer by activating this line. the drqr-pin remains high as long as the receiver fifo requires data transfers. only blocks of 32, 16, 8 or 4 bytes are transferred. 4 du7/ dackb1 i i i d ata u pstream iom-2 interface 7 / d ma- ack nowledge sacco channel b1 , active low. when low, this line notifies the sacco hdlc-channel, that the requested dma-cycle is in progress. together with rd (drqr) or wr (drqt) dack works like cs to enable a read or write operation to the top of the receive or the transmit fifo. when dack is active, the address lines are ignored and the fifos are implicitly selected. when dackb1 is not used the input line must be connected to v dd. table 1-1 iom ? -2 interface (contd) pin no. symbol in (i) out (o) during reset function peb 20560 overview semiconductor group 1-12 1997-11-01 note: the maximal input current on the following doc input lines will not exceed 2.3 ma at 5.5 v signal when the doc is without power supply (lines connected with the back plane): pfs, pdc2, pdc4, pdc8, xclk, refclk, rxd0 to rxd3, rxdb0, rxdb1, cxdb0, cxdb1, hfsb0 and hfsb1. (this is a protection for the case that a board with a doc is plugged into the pcm backplane and the doc is not yet connected to the power supply pins. refer to figure 6-1. ) table 1-2 pcm interface pin no. symbol in (i) out (o) during reset function 27 pfs i/o i p cm-interface f rames s ynchronization clock/ master clock 26 pdc2 i/o i p cm-interface d ata c lock / master clock 2.048 mhz 25 pdc4 i/o i pcm-interface data clock / master clock 4.096 mhz 24 pdc8 i/o i pcm-interface data clock / master clock 8.192 mhz 45 44 43 42 rxd0 rxd1 rxd2 rxd3 i i i i i receive pcm-interface data 41 40 39 38 txd0 txd1 txd2 txd3 o o o o high impedance transmit pcm-interface data 37 36 35 34 tsc0 tsc1 tsc2 tsc3 o o o o high tri-state control supplies a control signal for an external driver. these lines are low when the corresponding txd-outputs are valid. peb 20560 overview semiconductor group 1-13 1997-11-01 table 1-3 communication and signaling interfaces pin no. symbol in (i) out (o) during reset function sacco-b0 31 rxdb0 i i r eceive serial d ata hdlc-channel b0 . the serial data received on this line is forwarded into the corresponding hdlc-receive channel. data is sampled on the C falling edge of hdc (ccr2:rds = 0) or C rising edge of hdc (ccr2:rds = 1). 30 txdb0 o (od) high impedance t ransmit serial d ata hdlc-channel b0 . data output line of the corresponding hdlc-transmit channel. data is sampled on the bit ccr1:ods the pins have push pull or open drain characteristic. when transmission is disabled (tscb = 1) or when bit ccr2:txde is reset the pin is in the state high impedance. ( o pen d rain output.) 29 tscb0 o high t ri- s tate c ontrol hdlc-channel b0 , active low. supplies a control signal for an external driver. when low, the corresponding txd-outputs are valid. the detailed functionality is defined programming the sacco-registers ccr2:soc1,soc0. 28 cxdb0 i i c ollision d ata hdlc-channel b0 in a bus configuration, the external serial bus must be connected to the respective cxd pin for collision detection. in point-to-point configurations the pin provides a clear to send function. when 0/1 the transmit channel is enabled/disabled. if this function is not needed the pin has to be tied to v ss . peb 20560 overview semiconductor group 1-14 1997-11-01 uart 3 rxdu i i r eceive serial d ata on u art serial data input from the communications link (peripheral device, modem, or data set). 2 txdu o low t ransmit serial d ata on u art. this is the composite serial data output to the communications link (peripheral, modem or data set). this signal is set to the marking (logical 1 = 0) state upon a master reset operation. 1 rts o high r equest t o s end when low, this informs the modem or data set that the uart is ready to exchange data. the rts output signal can be set or reset by programming bit 1 (rts) of the modem control register. a master reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. table 1-3 communication and signaling interfaces (contd) pin no. symbol in (i) out (o) during reset function peb 20560 overview semiconductor group 1-15 1997-11-01 note: the optional sacco-b1 signals which are combined with iom-2 interface ports 4 to 7 are described in the table 1-1 . 160 cts ii cl ear t o s end when low, this indicates that the modem or data set is ready to exchange data. the cts signal is a modem status input whose conditions can be tested by the m p reading bit 4 (cts) of the modem status register. bit 4 is the complement of the cts signal. bit 0 (dcts) of the modem status register indicates whether the cts input has changed state since the previous reading of the modem status register. cts has no effect on the transmitter. note: whenever the cts bit of the modem status register changes state, an interrupt is generated if the modem status interrupt is enabled. other lines 88 chi o low ch annel i ndication signal on iom-2 79 drdy i i d -channel r ea dy controls sidec in lt-t mode applications (collision signal that the s/t interface is not free for signaling; i.e. quat-s signal) when not used this input should be tied to high. 152 fscd o high impedance f rame s ynchronization c lock with d elay of 62.5 m s related to the standard fsc (synchronizes layer-1 devices connected to the second half of an extended iom-2 interface with 64 time-slots; i.e. octat-p or quat-s). table 1-3 communication and signaling interfaces (contd) pin no. symbol in (i) out (o) during reset function peb 20560 overview semiconductor group 1-16 1997-11-01 table 1-4 dsp external memory interface pin no. symbol in (i) out (o) during reset function 153 cdpr o high c -bus d ata or p rogram r ead (active low) 154 cdpw o high c -bus d ata or p rogram w rite (active low) 155 cmbr o high c -bus m ail-box b oot r ead (active low) 156 cmbw o high c -bus m ail-box b oot w rite (active low) 159 cbr o high c -bus b oot r ead (active low) 123 122 121 120 117 116 115 114 111 110 109 108 104 103 102 101 cab15 cab14 cab13 cab12 cab11 cab10 cab9 cab8 cab7 cab6 cab5 cab4 cab3 cab2 cab1 cab0 o c -bus a ddress b us (cab0 = lsb) 128 cdb0/ boot i/o i i c -bus d ata b us bit 0 (lsb), during reset this pin is used as a strap, called boot. it enables the oak to execute the boot routine from internal boot rom.this routine loads a dsp program into the external program ram. refer to section 2.7.9 129 cdb1/ dbg i/o i i c -bus d ata b us bit 1 , dbg (debug) : during reset this pin is used as a strap. it may prevents reset of ocem registers when a reset is initiated by the debugger refer to section 2.7.9 130 cdb2/ rom i/o i i c -bus d ata b us bit 4 rom : during reset this pin is used as a strap. it enables boot from the cdi rom. refer to section 2.7.9 peb 20560 overview semiconductor group 1-17 1997-11-01 131 cdb3 i/o i c -bus d ata b us bit 3 . 134 cdb4/ urst i/o i c -bus d ata b us bit 2 , urst : user reset. during reset this pin is used as a strap. this option is used by the emulator. 135 cdb5 i/o i c -bus d ata b us bit 5 136 cdb6 i/o i c -bus d ata b us bit 6 137 cdb7 i/o i c -bus d ata b us bit 7 140 cdb8 i/o i c -bus d ata b us bit 8 141 cdb9 i/o i c -bus d ata b us bit 9 142 cdb10 i/o i c -bus d ata b us bit 10 143 cdb11 i/o i c -bus d ata b us bit 11 146 cdb12/ seibdis i/o i c -bus d ata b us bit 12 seibdis: seib disable. during reset this pin is used as a strap. 0 - serial emulation boot, via seib. 1 - parallel emulation boot. 147 cdb13 i/o i c -bus d ata b us bit 13 148 cdb14 i/o i c -bus d ata b us bit 14 149 cdb15 i/o i c -bus d ata b us bit 15 (msb) table 1-4 dsp external memory interface (contd) pin no. symbol in (i) out (o) during reset function peb 20560 overview semiconductor group 1-18 1997-11-01 1) shall the vcxo not be used, it is necessary to connect any other clock to this pin during reset. this clock is temporarily needed for resetting the internal units elic and sidec. 2) clk61 must always be connected as f/2 is needed for the doc internal topic. table 1-5 clock signals (additional to the iom ? -2, pcm and scc clocks) pin no. symbol in (i) out (o) during reset function 67 clk61 i i main clock of 61.44 mhz 1) 68 clk40-xi i i external dsp clock (0 40 mhz) 69 clk40-xo o o 70 clk16 i i vcxo clock of 16.384 mhz 2) 71 v vcxo oo 9 control oscillator (quartz) signal 72 clk30 o o 30.72 mhz ( m p clock) 73 clk15 o o 15.36 mhz (octat-p) 74 clk7 o o 7.68 mhz (quat-s) 75 xclk i i external synchronization clock (e.g. 1.536 mhz) 78 refclk i/o i reference clock (e.g. 512 khz) table 1-6 m p interface pin no. symbol in (i) out (o) during reset function 46 cs ii c hip s elect; active low. a low on this line selects all registers for read/write operations. 47 wr i i w rite, active low, identifies a write access. 48 rd i i r ead, active low 49 50 53 54 55 56 67 58 59 60 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 i/o i/o i/o i/o i/o i/o i/o i/o i i i i i i i i i i i i a ddress and d ata bus; multiplexed bus mode. handles addresses from the m p-system to the doc and transfers data between the m p and the doc. address bus peb 20560 overview semiconductor group 1-19 1997-11-01 note: after reset, ie0 remains in input direction. 100 ale i i a ddress l atch e nable ale controls the on chip address latch in multiplexed bus mode. while ale is high, the latch is transparent. the falling edge latches the current address. 61 ireq o (od) high i nterrupt req uest is programmable to active high or low. this signal is activated when the doc requests a cpu interrupt. due to open drain (od) characteristic of the output line multiple interrupt sources can be connected together. 62 iack ii i nterrupt ack nowledge 63 ie0 i/o i i nterrupt e nable 0 , 1 support lines for iack evaluation; depends of the selected mode (slave or daisy chain). 64 ie1 i i 80 resin o high res et in dication this pin is set to high, when the doc executes either a power-up reset, a watchdog timer reset, an external reset (dreset) or a software system reset. 81 dreset iC d oc reset a low forces the doc into reset state. table 1-6 m p interface (contd) pin no. symbol in (i) out (o) during reset function peb 20560 overview semiconductor group 1-20 1997-11-01 table 1-7 input / output port pin no. symbol in (i) out (o) during reset function 83 iop0 i/o i the i/o port is multifunctional and can be programmed to 3 different modes of use: mode 0: general purpose i/o port mode 1: sacco-b0 support lines. mode 2: uart support lines note: the signal names change accordingly. 84 iop1 i/o i 85 iop2 i/o i 86 iop3 i/o i mode 0: general purpose i/o port 83 port0 i/o i general purpose i/o lines during and after reset: mode 0 84 port1 i/o i 85 port2 i/o i 86 port3 i/o i mode 1: sacco-b0 support lines 83 drqtb0 o d ma- r e q uest t ransmitter sacco channel b0 the transmitter of hdlc-channel sacco requests a dma-data transfer by activating this line. the drqt-pin remains high as long as the transmit fifo requires data transfers. the number of data bytes to be transferred from system memory to the fifo must be written first into the xbch, xbcl registers (byte count registers). 84 drqrb0 o d ma- r e q uest r eceiver channel b0 the receiver of sacco channel requests a dma-data transfer by activating this line. the drqr-pin remains high as long as the receiver fifo requires data transfers. only blocks of 32, 16, 8 or 4 bytes are transferred. peb 20560 overview semiconductor group 1-21 1997-11-01 85 dackb0 i d ma- ack nowledge sacco channel b0, active low. when low, this line notifies the sacco hdlc-channel, that the requested dma-cycle is in progress. together with rd (drqr) or wr (drqt) dack works like cs to enable a read or write operation to the top of the receive or the transmit fifo. when dack is active, the address lines are ignored and the fifos are implicitly selected. when dackb0 is not used the pin must be connected to v dd . 86 hfsb0 i h dlc-interface f rame s ynchronization sacco channel b0 frame synchronization pulse in clock mode 2, data strobe in clock mode 1. mode 2: additional uart support lines 83 dsr i d ata s et r eady when low, this signal indicates that the modem or data set is ready to establish the communications link with the uart. the dsr signal is a modem status input whose condition can be tested by the cpu reading bit 5 (dsr) of the modem status register. bit 5 is the complement of the dsr signal. bit 1 (ddsr) of the modem status register indicates whether the dsr input has changed state since the previous reading of the modem status register. 1) table 1-7 input / output port (contd) pin no. symbol in (i) out (o) during reset function peb 20560 overview semiconductor group 1-22 1997-11-01 1) whenever the dsr bit etc. dcd bit of the modem status register changes state, an interrupt is generated if the modem status interrupt is enabled 84 dtr o d ata t erminal r eady when low, this informs the modem or data set that the uart is ready to establish a communications link. the dtr output signal can be set to an active low by programming bit 0 (dtr ) of the modem control register to a high level. a master reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. 85 ri i r ing i ndicator when low, this signal indicates that a telephone ringing signal has been received by the modem or data set. the rl signal is a modem status input whose condition can be tested by the cpu reading bit 6 (rl) of the modem status register. bit 6 is the complement of the rl signal. bit 2 (teri) of the modem status register indicates whether the rl input signal has changed from a low to a high state since the previous reading of the modem status register. note: whenever the rl bit of the modem status register changes from a high to a low state, an interrupt is generated if the modem status interrupt is enabled. 86 dcd i d ata c arrier d etect when low, it indicates that the data carrier has been detected by the modem or data set. the dcd signal is a modem status input whose condition can be tested by the cpu reading bit 7 (dcd) of the modem status register. bit 7 is the complement of the dcd signal. bit 3 (ddcd) of the modem status register indicates whether the dcd input has changed state since the previous reading of the modem status register. dcd has no effect on the receiver. 1) table 1-7 input / output port (contd) pin no. symbol in (i) out (o) during reset function peb 20560 overview semiconductor group 1-23 1997-11-01 table 1-8 power supply pin no. symbol in (i) out (o) function 16 pins: 17, 33, 52, 66, 77, 98, 106, 113, 119, 125, 127, 133, 139, 145, 151, 158. v dd i positive power supply + 3.3 v (for core logic) 107 v ddp i positive power supply + 5 v (for input protection and outputs) 15 pins: 16, 32, 51, 65, 76, 97, 105, 112, 118, 124, 126, 132, 138, 144, 150, 157. v ss i ground (0) table 1-9 test and emulation interfaces pin no. symbol in (i) out (o) during reset function test interface for boundary scan according to ieee std. 1149.1 89 jtclk i i j tag t est cl oc k 90 tms i i t est m ode s elect 91 tdi i i t est d ata i nput 92 tdo o spec. t est d ata o utput emulation interface and other control and test pins 95 dtclk o d sp t est cl oc k. (used for production test only) 96 stop o stop for external logic when using the ocem 99 abort i i low signal forces oak to stop program execution and to return control to the debugger 87 oak_test i i only for use for production testing. the oak_test pin has to be wired to v ss . peb 20560 overview semiconductor group 1-24 1997-11-01 82 sync i i internal doc sync hronization during reset and production tests. the sync pin has to be wired to v ss . 93 frq0 i i dsp fr e q uency selection: 00: dsp frequency = 20 mhz 01: dsp frequency = 30 mhz 10: dsp frequency = external dsp clock (e.g. 40 mhz) 11: only for production testing. 94 frq1 i i table 1-9 test and emulation interfaces (contd) pin no. symbol in (i) out (o) during reset function peb 20560 overview semiconductor group 1-25 1997-11-01 1.5 functional block diagram and system integration figure 1-6 functional block diagram and system integration its10072 r 2 arbiter 0 3 0 elic 1 2 3 -0 0 1 dcl, fsc, fscd -2 iom r epic r -0 watchdog sacco-a0 sacco-b0 elic 0 2 3 1 arbiter 1 1 sacco-b1 sacco-a1 3 2 r -1 0 mux pcm- logic sidec 0123 iom -mux r logic chi vcxo 16.384 mhz 40 mhz 61.44 mhz osc pll clock generator clk pdc2 pdc4 pdc8 pfs sidec elic r uart lnc rtc dsp dsp interface pcm- 2 x 32 ts 8 circular buffer reset sidec elic lnc dsp r doc-bus pn u peb 2465 -4 sicofi r 2 t/r t/r peb 2096 r octat -p 2 pn u 4 peb 2084 r quat -s s/t s/t subscribers d-channel control drdy xclk (e.g. 1.538 mhz) refclk (e.g. 512 khz) 7.68 mhz (quat r -s) 8.192 mhz (e.g. falc 15.36 mhz (octat -p) r box mail (lnc) timer dsp siemens oak data 1 k x 16 memory memory data 512 x 16 ocem dcu rom boot bus mux p & d state wait uart c-bus interface m p controller interrupt i/o port universal lnc sacco-b1 0 1 2 3 4 5 6 7 epic r -1 mpu-clock jtag 8 8 16 (a-/ m -law) xy p-bus d-bus 3 2 1 0 4(8) pcm highways pfs, pdc2, pdc4, pdc8 pcm highways with up to 4 x 32 ts = 4 x 2.048 mbit/s or 4 x 64 ts = 4 x 4.096 mbit/s or 4 x 128 ts = 2 x 8.192 mbit/s signaling 5 v 3.3 v external program and data memory 16-bit program and data bus 4 v.24 (5) local network dreset resin test 4 ireq iack ie0, ie1 i/o 2 4 (3) dma m p-bus p m and data program memory controller interrupt falc clk munich32 r iom -2/pcm doc e1 / t1 x tm 54) tm 54 i/o controller 16 16 peb 20560 overview semiconductor group 1-26 1997-11-01 1.6 example for system integration figure 1-7 example for a pbx with one doc its10073 r octat -p u pn -s quat r s/t r sicofi t/r -4 iom -2 r doc peb 20560 oak jtag 40 c-bus external dsp memory memory m p i/o 10 scdi pc board pxb board peb 20560 functional block description semiconductor group 2-1 1997-11-01 2 functional block description doc block diagram and system integration see figure 1-3 . 2.1 elic0 and elic1 2.1.1 general functions and device architecture the elic integrates the existing siemens device peb 2055 (epic-1), a two channel hdlc-controller (sacco: special application communication controller) with a peb 2050 (pbc) compatible auto-mode, a d-channel arbiter, a configurable bus interface and typical system glue logic into one chip. it covers all control functions on digital and analog line cards and can be combined via iom-2 interface with layer-1 circuits or special application devices (e.g. adpcm/pcm-converters). 2.1.2 functional blocks 2.1.2.1 watchdog timer to allow recovery from software or hardware failure, a watchdog timer is provided. after reset the watchdog timer is disabled. when setting bit swt in the watchdog timer control register wtc it is enabled. the only possibility to disable the watchdog timer is a elic-reset (power-up or dreset ).the timer period is 1024 pfs-cycles assuming that also pdc is active, i.e. a pfs of 8-khz results in a timer period of 128 ms. during that period, the bits wtc1 and wtc2 in the register wtc have to be written in the following sequence: the minimum required interval between the two write accesses is 2 pdc-periods. when the software fails to follow these requirements, a timer overflow occurs and a iwd-interrupt is generated. additionally an external reset indication (resin) is activated. the internal elic-status is not changed. table 2-1 watchdog timer programming activity wtc:wtc1 wtc:wtc2 1. 1 0 2. 0 1 peb 20560 functional block description semiconductor group 2-2 1997-11-01 2.1.2.2 reset logic after power-up the elic is latched into the resetting state. therefor an integrated power-up reset generator is provided. additionally an external reset input (dreset ) and an reset indication output (resin) are available. a microprocessor access is not possible in the resetting state. the elic is released from the power-up resetting state when provided with pfs- and pdc-signals for 8 pfs-periods. the elic can also be reset by applying a dreset -pulse for at least 4 pdc-periods. note that such an external dreset has priority over a power-on reset. it is thus possible to kill the 8-frame reset duration after power-up. for correct dreset a main clock must be applied to clk61. during reset all elic-outputs with the exception of resin and tdo + drqra/b + drqta/b + sacco are in the state high impedance. the tri-state control signals of the epic-1 pcm-interface (tsc [3:0]) tsca /b are not tri-stated during a chip reset. instead they are high during reset, thus containing the correct tri-state information for external drivers. resin is set upon power up, dreset and the expiring of the watchdog timer. it may be used as a system reset. resin is activated for 8 pfs-periods (assuming an active pdc-input) or it has the same pulse width as dreset . dreset has priority over internal generated resets with respect to the resin pulse width. the activation of dreset causes an immediate activation of resin. upon the deactivation of dreset however, resin is deactivated only with the next rising pdc-edge. a pfs-frequency of 8-khz results in a resin-period of 1 ms. when setting bit vnsr:swrx resin is also activated but the elic itself is not reset. this feature supports a proper reset procedure for devices which require dedicated clocking during reset. the sequence required is as follows: 1. initialize epic-1 for a timer interrupt 2. set bit vnsr:swrx to 1, resin is activated 3. when the timer interrupt occurs, resin is deactivated 4. set bit vnsr:swrx to 0 5. read ista_e, in order to deactivate timer interrupt table 2-2 reset activities internal elic reset resin activation resin pulse width power up x x 8 pfs watchdog timer under flow C x 8 pfs external reset (dreset ) x x dreset setting of bit swrx C x programmable peb 20560 functional block description semiconductor group 2-3 1997-11-01 when v dd drops under normal operation the reset logic has the following behavior: note: the power-up reset generator must not be used as a supply voltage control element. 2.1.2.3 epic ? -1 2.1.2.3.1 pcm-interface the pcm-interface formats the data transmitted or received at the pcm-highways. it can be configured as one (max. 8.192 mbit/s), two (max. 4.096 mbit/s) or four (max. 2.048 mbit/s) pcm-ports, consisting each of a data receive (rxd#), a data transmit (txd#) and an output tri-state indication line (tsc# ). port configuration, data rates, clock shift and sampling conditions are programmable. the newly implemented pcm-mode 3 is similar to mode 1 (two pcm-highways). unlike mode 1 the pins txd1, txd3 are not tri-stated but drive the inverted values of txd0, txd2. 2.1.2.3.2 configurable interface in order to optimize the on-board interchip communication, a very flexible serial interface is available. it formats the data transmitted or received at the ddn-, dun- or sipn-lines. although it is typically used in iom-2 or sld-configuration to connect layer-1 devices, application specific frame structures can be defined (e.g. to interface adpcm-converters or maintenance blocks). 2.1.2.3.3 memory structure and switching the memory block of the epic-1 performs the switching functionality. it consists of four sub blocks: C upstream data memory C downstream data memory C upstream control memory C downstream control memory table 2-3 behavior of the reset logic in the case of voltage drop v dd behavior > 3 v no internal reset, no resin < 1 v internal reset and resin after v dd goes up again 1 v v dd 3 v not defined peb 20560 functional block description semiconductor group 2-4 1997-11-01 the pcm-interface reads periodically from the upstream (writes periodically to the downstream) data memory (cyclical access), see figure 2-1 . the cfi reads periodically the control memory and uses the extracted values as a pointers to write to the upstream (read from the downstream) data memory (random access). in the case of c/i- or signaling channel applications the corresponding data is stored in the control memory. in order to select the application of choice, the control memory provides a code portion. the control memory is accessible via the m p-interface. in order to establish a connection between cfi time-slot a and pcm-interface time-slot b, the b-pointer has to be loaded into the control memory location a. 2.1.2.3.4 pre-processed channels, layer-1 support the epic-1 supports the monitor/feature control and control/signaling channels according to sld- or iom-2 interface protocol. the monitor handler controls the data flow on the monitor/feature control channel either with or without active handshake protocol. to reduce the dynamic load of the cpu a 16-byte transmit/receive fifo is provided. the signaling handler supports different schemes (d-channel + c/i-channel, 6-bit signaling, 8-bit signaling). in downstream direction the relevant content of the control memory is transmitted in the appropriate cfi time-slot. in the case of centralized isdn d-channel handling, a 16-kbit/s d-channel received at the pcm-interface is included. in upstream direction the signaling handler monitors the received data. upon a change it generates an interrupt, the channel address is stored in the 9-byte deep c/i fifo and the actual value is stored in the control memory. in 6-bit and 8-bit signaling schemes a double last look check is provided. peb 20560 functional block description semiconductor group 2-5 1997-11-01 . figure 2-1 epic ? -1 memory structure 2.1.2.3.5 special functions C synchronous transfer. this utility allows the synchronous m p-access to two independent channels on the pcm- or cfi-interface. interrupts are generated to indicate the appropriate access windows. C 7-bit hardware timer. the timer can be used to cyclically interrupt the cpu, to determine the double last look period, to generate a proper cfi-multiframe synchronization signal or to generate a defined resin pulse width. C frame length checking. the pfs-period is internally checked against the programmed frame length. C alternative input functions. in pcm-mode 1 and 2, the unused ports can be used for redundancy purposes. in these modes, for every active input port a second input port exists which can be connected to a redundant pcm-line. additionally the two lines are checked for mismatches. its05823 data 8 bits code 4 bits 4 bits code 8 bits data 0 ... 127 data memory (dm) control memory (cm) 0 ... 127 data 8 bits data memory (dm) 0 ... 127 127 ... 0 (cm) memory control data 8 bits code 4 bits txd# rxd# pcm du# dd# cfi p upstream downstream peb 20560 functional block description semiconductor group 2-6 1997-11-01 2.1.2.4 sacco the sacco (special application communication controller) is a high level serial communication controller consisting of two independent hdlc-channels (a + b). it is a derivative product of the siemens sab 82525 (hscx). the sacco essentially reduces the hardware and software overhead for serial synchronous communication. sacco channel a can be multiplexed by the d-channel arbiter to serve multiple subscribers. in the following section one sacco channel is described referring to as sacco. 2.1.2.4.1 block diagram the sacco (one channel) provides two independent 64-byte fifos for receive and transmit direction and a sophisticated protocol support. it is optimized for line card applications in digital exchange systems and offers special features to support: C communication between a line card and a group controller C communication between terminal equipment and a line card 2.1.2.4.2 parallel interface all registers and the fifos are accessible via the doc parallel m p-interface. the fifos allocate an address space of 32 bytes each. the data in the fifos can be managed by the cpu- or a dma-controller. to enable the use of block move instructions, the top of fifo-byte is selected by any address in the reserved range. interrupts the sacco indicates special events by issuing an interrupt request. the cause of a request can be determined by reading the interrupt status register ista_a/b or exir_a/b. the related register is flagged in the top level ista (refer to figure 3-1 ). three indications are available in ista_a/b, another five in the extended interrupt register exir_a/b. an interrupt which is masked in the mask_a/b is not indicated in the top level register and the int -line is not activated. the interrupt is also not visible in the local registers ista_a/b but remains stored internally and will be indicated again when the corresponding mask_a/b-bit is reset. the sacco-interrupt sources can be splitted in three logical groups: ? receive interrupts (rfs, rpf, rme, ehc) ? transmit interrupts (xpr, xmr) ? special condition interrupts (xdu/exe, rfo) for further information refer to chapter 3.1.4.1 (data transmission in interrupt mode) and chapter 3.1.4.3 (data reception in interrupt mode). peb 20560 functional block description semiconductor group 2-7 1997-11-01 dma-interface to support efficient data exchange between system memory and the fifos an additional dma-interface is provided. the fifos have separate dma-request lines (drqra/b for rfifo, drqta/b for xfifo) and a common dma-acknowledge input. the dma-controller has to operate in the level triggered, demand transfer mode. if the dma-controller provides a dma-acknowledge signal, each bus cycle implicitly selects the top of fifo and neither address nor chip select is evaluated. if no dack signal is supplied, normal read/write operations (providing addresses) must be performed (memory to memory transfer). the sacco activates the drqt/r-lines as long as data transfers are needed from/to the specific fifos. a special timing scheme is implemented to guarantee safe dma-transfers regardless of dma-controller speed. if in transmit direction a dma-transfer of n bytes is necessary (n < 32 or the remainder of a long message), the drqt-pin is active up to the rising edge of wr of dma-transfer (n-1). if n > 32 the same behavior applies additionally to transfers 31, 63, , ((k 32) - 1). drqt is activated again with the next rising edge of dack (or css ), if there are further bytes to transfer ( figure 2-3 ). when a fast dma-controller is used (> 16 mhz), byte n (or bytes k 32) will be transferred before drqt is deactivated from the sacco. in this case pin drqt is not activated any more up to the next block transfer ( figure 2-2 ). figure 2-2 timing diagram for dma-transfers (fast) transmit (n < 32, remainder of a long message or n = k 32) itd05825 drqt wr css, dack cycle n-2 n-1 n peb 20560 functional block description semiconductor group 2-8 1997-11-01 figure 2-3 timing diagram for dma-transfers (slow) transmit (n < 32, remainder of a long message or n = k 32) in receive direction the behavior of pin drqr is implemented correspondingly. if k 32 bytes are transferred, pin drqr is deactivated with the rising edge of rd of dma-transfer ((k 32) - 1) and it is activated again with the next rising edge of dack (or css ), if there are further bytes to transfer ( figure 2-5 ). when a fast dma-controller is used (> 16 mhz), byte n (or bytes k 32) will be transferred immediately ( figure 2-4 ). however, if 4, 8, 16 or 32 bytes have to be transferred (only these discrete values are possible in receive direction), drqr is deactivated with the falling edge of rd ( figure 2-6 ). figure 2-4 timing diagram for dma-transfer (fast) receive (n = k 32) figure 2-5 timing diagram for dma-transfers (slow) receive (n = k 32) itd05826 drqt wr css, dack cycle n-2 n-1 n itd05827 drqr rd css, dack cycle n-2 n-1 n itd05828 drqr rd css, dack cycle n-2 n-1 n peb 20560 functional block description semiconductor group 2-9 1997-11-01 figure 2-6 timing diagram for dma-transfers (slow or fast) receive (n = 4, 8 or 16) generally it is the responsibility of the dma-controller to perform the correct bus cycles as long as a request line is active. for further information refer to chapter 3.1.4.2 (data transmission in dma-mode) and chapter 3.1.4.4 (data reception in dma-mode) . figure 2-7 dma-transfers with pulsed dack (read or write) if a pulsed dack-signal is used the drqr/drqt-signal will be deactivated with the rising edge of rd/wr-operation (n - 1) but activated again with the following rising edge of dack. with the next falling edge of dack (dack n) it will be deactivated again (see figure 2-7 ). this behavior might cause a short negative pulse on the drqr/drqt-line depending on the timing of dack vs. rd /wr . itd05829 drqr rd css, dack cycle n-2 n-1 n drqr / drqt dack wr / rd n n-1 n-2 itd06896 peb 20560 functional block description semiconductor group 2-10 1997-11-01 2.1.2.4.3 fifo-structure two independent 64-byte deep fifos for transmit and receive direction are provided. they enable an intermediate storage of data between the serial and the parallel (cpu) interface. the fifos are divided into two halves of 32 bytes each, where only one half is accessible by the cpu- or dma-controller. receive fifo the receive fifo (rfifo) is organized in two parts of 32 bytes each, of which only one part is accessible for the cpu. when a frame with up to 64 bytes is received, the complete frame may be stored in rfifo. after the first 32 bytes have been received, the sacco prompts to read the data block by means of interrupt or dma-request (rpf-interrupt or activation of drqr-line). the data block remains in the rfifo until a confirmation is given to the sacco-acknowledging the reception of the data. this confirmation is either a rmc- (receive message complete) command in interrupt mode or it is implicitly achieved in dma-mode after 32 bytes have been read. as a result it is possible in interrupt mode to read out the data block any number of times until the rmc-command is executed. upon the confirmation the second data block is shifted into the accessible rfifo-part and an rme-interrupt is generated. the configuration of the rfifo prior to and after acknowledgment is shown in figure 2-8 ( left ). if frames longer than 64 bytes are received, the sacco will repeatedly prompt to read out 32-byte data blocks via interrupt or dma. figure 2-8 frame storage in rfifo (single frame / multiple frames) free last block of frame i to acknowledgement rfifo status prior rfifo status prior to acknowledgement cpu accessible 32 bytes fifo part, 32 bytes block b frame j rfifo status after acknowledgement free block b+1 free acknowledgement rfifo status after frame i+1 itd05830 free frame i+n frame i+1 cpu inaccessible fifo part, 32 bytes block b+1 frame j free free free frame i+n frame i+2 0 < n < 17 peb 20560 functional block description semiconductor group 2-11 1997-11-01 in the case of several shorter frames , up to 17 frames may be stored in the rfifo. nevertheless, only one frame is stored in the cpu accessible part of the rfifo. e.g., if frame i (or the last part of frame i) is stored in the accessible rfifo-part, up to 16 short frames may be stored in the other half (i + 1, i + 2, , i + n, n 16). this behavior is illustrated in figure 2-8 ( right ). note: after every frame a receive status byte is appended, specifying the status of the frame (e.g. if the crc-check is o.k.). when using the dma-mode, the sacco requests fixed size block transfers (4, 8, 16 or 32 bytes). the valid byte count is determined by reading the registers rbch, rbcl following the rme-interrupt. transmit fifo the transmit fifo (xfifo) provides a 2 32 bytes capability to intermediately store transmit data. in interrupt mode the user loads the data and then executes a transmit command. when the frames are longer than 32 bytes, a xpr-interrupt is issued as soon as the accessible xfifo-part is available again. the status of the bit mode:cft (continuous frame transmission) defines whether a new frame can be loaded as soon as the xfifo is available or after the current transmission was terminated. figure 2-9 xfifo loading, continuous frame transmission disabled (cft = 0) itd05831 xpr xpr xpr xpr frame transmission transmit serial data frame n frame n+1 frame n frame n+1 (40 bytes) copy data to inaccessable xfifo part frame preparation cmd : xtf write xfifo (32 bytes) write xfifo cmd : xtf+xme write xfifo cmd : xtf+xme (32 bytes) (8 bytes) (32 bytes) peb 20560 functional block description semiconductor group 2-12 1997-11-01 figure 2-10 xfifo loading, continuous frame transmission enabled (cft = 1) when using the dma-mode, prior to the data transfer the actual byte count to be transmitted must be written to the registers xbch, xbcl (transmit byte count high, low). if the data transfer is initiated via the proper command, the sacco automatically requests the correct amount of block data transfers (n 32 + remainder, n = 0, 1, 2, ) by activating the drqt-line. refer to chapter 2.1.2.4.2 for a detailed description of the dma transfer timing. 2.1.2.4.4 protocol support the sacco supports the following fundamental hdlc functions: C flag insertion/deletion, C bit stuffing, C crc-generation and checking, C address recognition. further more it provides six different operating modes, which can be set via the mode register. these are: C auto mode, C non-auto mode, C transparent mode 0 and 1, C extended transparent mode 0 and 1. these modes provide different levels of hdlc processing. itd05832 xpr xpr xpr xpr frame transmission transmit serial data frame n frame n+1 frame n frame n+1 (40 bytes) copy data to inaccessable xfifo part frame preparation cmd : xtf write xfifo (32 bytes) write xfifo cmd : xtf+xme write xfifo (32 bytes) (8 bytes) (32 bytes) frame n+2 xpr (32 bytes) write xfifo frame n+2 cmd : xtf+xme cmd : xtf+xme peb 20560 functional block description semiconductor group 2-13 1997-11-01 . figure 2-11 support of the hdlc protocol by the sacco address recognition address recognition is performed in three operating modes (auto-mode, non-auto-mode and transparent mode 1). two pairs of compare registers (rah1, rah2: high byte compare, ral1, ral2: low byte compare) are provided. ral2 may be used for a broadcast address. in auto-mode and non-auto-mode 1- or 2-byte address fields are supported, transparent mode 1 is restricted on high byte recognition. the high byte address is additionally compared with the lapd group address (fc h , fe h ). itd08035 flag address control field crc flag i- sacco user auto mode non-auto mode transparent mode 1 extended transparent mode transparent mode 0 peb 20560 functional block description semiconductor group 2-14 1997-11-01 depending on the operating mode the following combinations are considered valid addresses: table 2-4 address recognition operating mode compare value high byte compare value low byte activity auto-mode, 2-byte address field peb 20560 functional block description semiconductor group 2-15 1997-11-01 auto-mode (mode:mds1,mds0 = 00) characteristics: hdlc formatted, nrm-type protocol, 1-byte/2-byte address field, address recognition, any message length, automatic response generation for rr- and i-frames, window size 1. the auto-mode is optimized to communicate with a group controller following a nrm- (normal response mode) type protocol. its functionality guarantees a minimum response time and avoids the interruption of the cpu in many cases. the sacco auto-mode is compatible to a peb 2050 (pbc) behavior in secondary mode. following the pbc-conventions, two data types are supported in auto-mode. note: in many applications only direct data is used, nevertheless both data types are supported because of compatibility reasons. receive direction in auto-mode the sacco provides address recognition for 2- and 1-byte address fields. the auto-mode protocol is only applied when ral1 respectively rah1/ral1 match. with any other matching combination, the frame is transferred transparently into the rfifo and an interrupt (rpf or rme) is issued. if no address match occurs, the frame is skipped. the auto-mode protocol processes rr- and i-frames automatically. on the reception of any other frame type an ehc-interrupt (extended hdlc frame) is generated. no data is stored in the rfifo but due to the internal hardware structure the hdlc-control field is temporarily stored in register rhcr. in the pbc-protocol an extended hdlc-frame does not contain any data. table 2-5 auto-mode data types data types meaning direct data data exchanged in normal operation mode between the local m p and the group controller, typically signaling data. prepared data data request by or send to the group controller for maintenance purposes. table 2-6 hdlc-control field in auto-mode hdlc-control byte frame type xxxp xxx0 i-frame xxxp xx01 rr-frame xxxx xx11 extended hdlc-frame peb 20560 functional block description semiconductor group 2-16 1997-11-01 rr-frames rr-frames are processed automatically and are not stored in rfifo. when a rr-frame with poll bit set (control field = xxx10001) is received, it is interpreted as a request to transmit direct data. depending on the status of the xfifo an i-frame (data available) or a rr-response (no data available) is issued. this behavior guarantees minimum response times and supports a fast cyclical polling of signaling data in a point-to-multi-point configuration. a rr-frame with poll bit = 0 is interpreted as an acknowledgment for a previously transmitted i-frame: the xfifo is cleared, a xpr interrupt is emitted, no response is generated. the polling of a frame can be repeated an unlimited number of times until the frame is acknowledged. depending on the status of the bit mode:arep (auto repeat), the transmission is repeated without or with the intervention of the cpu (xmr interrupt). the auto repeat mode must not be selected, when the frame length exceeds 32 bytes. in dma mode, when using the auto repeat mode, the control response will not be compatible to the pbc. i-frames when an i-frame is received in auto-mode the first data byte is interpreted as a command byte according to the peb 2050 (pbc) protocol. depending on the value of the command byte one of the following actions is performed. table 2-7 auto-mode command byte interpretation command byte = 1. data byte stored in rfifo interrupt additional activities condition 00 - 9f h b0 - cf h f0 - ff h yes rpf, rme response generation when poll bit set C a0-af h no no response generation when poll bit set i-frame with xfifo-data C command xpd executed d0 - ef h no xpr response generation when poll bit set, reset xfifo command xpd executed no no response generation when poll bit set command xpd not executed peb 20560 functional block description semiconductor group 2-17 1997-11-01 when a i-frame is stored in rfifo the command byte has to be interpreted by software. depending on the subset of pbc commands used in the individual application, the implementation may be limited to the necessary functions. in case xpd is executed (with or without data in xfifo) the sacco will generate an xpr interrupt upon the reception of a command d0 h , , ef h , even if the data has not been polled previously. note: in auto-mode i-frames with wrong crc or aborted frames are stored in rfifo. in the attached rsta-byte the crc and rab-bits are set accordingly to indicate this situation. in these cases no response is generated. transmit direction, response generation in auto-mode frames are only transmitted after the reception of a rr- or i-frame with poll bit set. rr-response the rr-response is generated automatically. it has the following structure. the address is defined by the value stored in xad1 (1-byte address) or xad1 and xad2 (2-byte address). the control byte is fixed to 11 h (rr-frame, final bit = 1). control response the control response is generated automatically. it has the following structure. table 2-8 auto-mode response generation received frame response condition rr-poll poll bit set i-frame with xfifo-data command xdd executed rr-response command xdd not executed i-frame, first byte = axh poll bit set i-frame with xfifo-data command xpd executed i-frame, data byte = control response command xpd not executed i-frame, first data byte not axh, poll bit set i-frame, data byte = control response flag address control byte crc-word flag flag address control byte control resp. crc-word flag peb 20560 functional block description semiconductor group 2-18 1997-11-01 the address is defined by the value stored in xad1 (1-byte address) or xad1 and xad2 (2-byte address). the control byte is fixed to 10 h . according to the pbc conventions, the control response byte has the following structure: bit76 : 10 : response to an i-frame, no further data follows bit5 : 1 : m p connected (pbc operates optionally in stand alone mode) bit4 : arep : 1/0: autorepeating is enabled/disabled (read back value of cmdr:arep) bit32 : 00 : sacco fifo available for data reception bit1 : dov : inverted status of the bit rsta:rdo (rfifo overflow) bit0 : 1 : fixed value, no functionality. i-frame with data the address is defined by the value stored in xad1 (1-byte address) or xad1 and xad2 (2-byte address). the control byte is fixed to 10 h (i-frame, final bit = 1). the data field contains the xfifo contents. note: the control response byte has to be generated by software. data transfer polling of direct data when direct data was loaded (xdd executed) an i-frame is generated as a response to a rr-poll. after checking star:xfw, blocks of up to 32 bytes may be entered in xfifo. when more than 32 bytes are to be transmitted the xpr-interrupt is used to indicate that the cpu accessible xfifo-part is free again. a maximum of 64 bytes may be stored before the actual transmission is started. a rr-acknowledge (poll bit = 0) causes an ista:xpr interrupt, xfifo is cleared and star:xfw is set. when the sacco receives a rr-poll frame and no data was loaded in xfifo it generates automatically a rr-response. bit 7 bit 0 1 0 1 arep 0 0 dov 1 flag address control byte data crc-word flag peb 20560 functional block description semiconductor group 2-19 1997-11-01 figure 2-12 polling of up to 64 bytes direct data if more than 64 bytes are transmitted, the xfifo is used as an intermediate buffer. data has to be reloaded after transmission was started. figure 2-13 polling more than 64 bytes of direct data (e.g. 96 bytes) its05833 wr xfifo cmdr : xdd ista : xpr wr xfifo cmdr : rr-poll complete i-frame sacco slave group controller master (pbc) xdd/xme gc polls, data is available, the slave sends an i-frame. ista : xpr rr-acknowledge rr-poll rr-response be loaded. interrupt, new data can the slave emits an xpr gc acknowledges, gc polls, no data is available, the slave generates a rr-response. its05834 rr-poll complete i-frame group controller master (pbc) gc polls, data is available, the slave sends an i-frame, data has to be reloaded during transmission. ista : xpr wr xfifo ista : xpr cmdr : xdd wr xfifo slave sacco wr xfifo cmdr : xdd/xme cmdr : xdd peb 20560 functional block description semiconductor group 2-20 1997-11-01 when the group controller wants the sacco to re-transmit a frame (e.g. due to a crc-error) it does not answer with a rr-acknowledge but emits a second rr-poll. the sacco then generates an xmr-interrupt (transmit message repeat) indicating the cpu that the previously transmitted frame has to be loaded again. for frames which are not longer then 32 bytes the sacco offers an auto repeat function allowing the automatic re-transmission of a frame without interrupting the cpu. note: for frames which are longer than 32 bytes the auto repeat function must not be used. figure 2-14 re-transmission of a frame its05835 rr-poll complete i-frame sacco slave group controller master (pbc) gc polls, data is available, the slave sends an i-frame, data is corrupted, gc polls again, sacco emits xmr. rr-poll e.g. crc error exir : xmr cmdr : xdd/xme wr xfifo ista : xpr cmdr : xdd wr xfifo peb 20560 functional block description semiconductor group 2-21 1997-11-01 figure 2-15 re-transmission of a frame with auto-repeat function polling of prepared data if polling prepared data a different procedure is used. the group controller issues an i-frame with a set poll bit and the first data byte is interpreted as command byte. when prepared data was loaded into the xfifo (cmdr:xpd/xme was set) the reception of a command byte equal to axh initiates the transmission of an i-frame. for prepared data the auto repeat function must be selected! due to this the polling can be repeated without interrupting the cpu. an i-frame with a data byte equal to d0h-efh is interpreted as an acknowledgment for previously transmitted data. an xpr-interrupt is issued and the xfifo is reset. all other i-frames are stored in the rfifo and a rme-interrupt is generated. the local m p can read and interpret the received data (e.g. following the pbc-protocol). a pbc compatible control response is generated automatically. e.g., if the local m p recognizes the request to prepare data it may load the xfifo and set cmdr:xpd/xme. its05836 sacco slave group controller master (pbc) gc polls, data is available, the slave sends an i-frame, data is corrupted, gc polls again, sacco retransmits, rr-poll complete i-frame complete i-frame rr-poll rr-acknowledge e.g. crc error gc acknowledges, sacco emits xpr. ista : xpr xdd/xme/arep cmdr : wr xfifo peb 20560 functional block description semiconductor group 2-22 1997-11-01 figure 2-16 polling of prepared data behavior of sacco when a rfifo overflow occurs in auto-mode when the rfifo overflows during the reception of an i-frame, a control response with overflow indication is transmitted, the overflow information is stored in the corresponding receive status byte. when additional poll frames are received while the rfifo is still occupied, an rfo (receive frame overflow) interrupt is generated. depending on the type of the received poll frame different responses are generated: i-frame C control response with overflow indication (exception: when the command transmit prepared data (axh) is received and prepared data is available in the xfifo, an i-frame (with data) is issued) rr-poll C rr-response, when no direct data was stored in the xfifo C i-frame, when direct data was stored in the xfifo its05837 control resp. group controller master (pbc) e.g. crc error i-frame (prepare data) complete i-frame i-frame (ax ) i-frame (d0 ) gc emits an i-frame with a command byte requesting the preparation of a defined data type. the command has to be interpreted by software, a response is generated automatically. gc uses the command ax to poll the requested data. the slave reacts without interrupting gc uses the command d0 -ef to acknowledge received data. the slave issues a xpr interrupt. ista : xpr cmdr : xpd/ wr xfifo rd rfifo slave sacco ista : rme xme/arep the cpu. h h hh h peb 20560 functional block description semiconductor group 2-23 1997-11-01 depending on the number of bytes to be stored in the rfifo the following behavior occurs: multiple shorter frames results in the same behavior, e.g. frame 1: 1-31 bytes frame 2 - n: total of 31 bytes including receive status bytes for frame 2 - (n - 1) cause the case 1. table 2-9 rfifo handling/steps case 1 case 2 case 3 receive frame total frame length: 63 data bytes total frame length: 64 data bytes total frame length: 65 data bytes or more after 32 bytes are received a rpf-interrupt is issued, the rfifo is not acknowledged after next 31/32 bytes are received control response, no overflow indication control response with overflow indication control response with overflow indication additional i-poll rfo-interrupt, i-response with overflow indication or i-data if stored in xfifo as prepared data additional rr-poll rfo-interrupt, rr-response or i-data if stored in xfifo as direct data read and acknowledge rfifo rme-interrupt rpf-interrupt rpf-interrupt read and acknowledge rfifo rdo-bit is not set, frame is complete rme-interrupt rme-interrupt read and acknowledge rfifo rdo-bit is set, frame is complete but indicated as incomplete rdo-bit is set, frame is not complete peb 20560 functional block description semiconductor group 2-24 1997-11-01 non-auto-mode (mode:mds1, mds0 = 01) characteristics: hdlc formatted, 1-byte/2-byte address field, address recognition, any message length, any window size. all frames with valid address fields are stored in the rfifo and an interrupt (rpf, rme) is issued. the hdlc-control field, data in the i-field and an additional status byte are stored in rfifo. the hdlc-control field and the status byte can also be read from the registers rhcr, rsta (currently received frame only!). according to the selected address mode, the sacco can perform 2-byte or 1-byte address recognition. transparent mode 1 (mode:mds1, mds0, adm = 101) characteristics: hdlc formatted, high byte address recognition, any message length, any window size. only the high byte address field is compared with rah1, rah2 and the group address (fc h , fe h ). the whole frame except the first address byte is stored in rfifo. ral1 contains the second and rhcr the third byte following the opening flag (currently received frame only). when using lapd the high byte address recognition feature can be used to restrict the frame reception to the selected sapi-type. transparent mode 0 (mode:mds1, mds0, adm = 100) characteristics: hdlc formatted, no address recognition, any message length, any window size. no address recognition is performed and each frame is stored in the rfifo. ral1 contains the first and rhcr the second byte following the opening flag (currently received frame only). note: in non-auto-mode and transparent mode i-frames with wrong crc or aborted frames are stored in rfifo. in the attached rsta-byte the crc and rab-bits are set accordingly to indicate this situation. peb 20560 functional block description semiconductor group 2-25 1997-11-01 extended transparent mode 0 (mode:mds1, mds0, adm = 110) characteristics: fully transparent without hdlc framing, any message length, any window size. data is stored in register ral1. in extended transparent mode, fully transparent data transmission/reception without hdlc-framing is performed, i.e. without flag-generation/recognition, crc-generation/check, bit stuffing mechanism. this allows user specific protocol variations or can be used for test purposes (e.g. to generate frames with wrong crc-words). data transmission is always performed out of the xfifo. data reception is done via register ral1, which contains the actual data byte assembled at the rxd pin. extended transparent mode 1 (mode:mds1, mds0, adm = 111) characteristics: fully transparent without hdlc-framing, any message length, any window size. data is stored in register ral1 and rfifo. identical behavior as extended transparent mode 0 but the received data is shifted additionally into the rfifo. receive data flow (summary) the following figure gives an overview of the management of the received hdlc-frames depending on the selected operating mode. peb 20560 functional block description semiconductor group 2-26 1997-11-01 figure 2-17 receive data flow note: rr-frames and i-frame with first data byte equal to ax h or d0 h -ef h are processed automatically. they are not stored in rfifo and no interrupt is issued. ral 2 compared with register/group address processed automatically stored in rfifo, register non automode/16 adm adm non automode/8 transparent mode 1 adm adm transparent mode 0 mds 1 1 mds 0 00 mds 1 1 mds 1 0 mds 0 01 mds 0 10 mds 1 0 mds 0 11 feh ral 1 rhcr rfifo ral 1 ral 2 rah 2 or fch or ral 1 ral 2 rah 1 rah 2 fch feh ral 1 x rah 1 or rah 1 or fch or rah 2 or feh x rhcr rhcr rhcr rhcr broadcast hdlc frame itd05838 rsta rfifo rfifo rsta rsta rfifo rfifo rsta rsta flag adm adm automode/8 mds 1 0 mds 0 00 automode/16 0 mds 1 1 0 mds 0 1 ral 1 ral 1 ral 2 rah 2 or fch or ral 1 ral 1 feh x x rah rah 2 or fch or rah 1 or feh 1 rhcr rhcr xxxxxx11 x0 h rhcr rhcr rhcr xxxxxx11 ral 1 address rah 1 addr control x0 h ctrl data 1. byte i i-frame, 1. data byte note : compressed hdlc control field stored in rhcr extended hdlc frame broadcast hdlc frame extended hdlc frame i-frame, 1. data byte note : compressed hdlc control field stored in rhcr rfifo rsta rsta rfifo rsta rsta rsta not ax or do -ef hh status data rfifo i not ax or do -ef h crc h flag h h peb 20560 functional block description semiconductor group 2-27 1997-11-01 2.1.2.4.5 special functions cyclical transmission (fully transparent) when the extended transparent mode is selected, the sacco supports the continuous transmission of the xfifo-contents. after having written 1 to 32 bytes to the xfifo, the command xrep/xtf/xme (xrep/xtf in dma-mode) is executed. consequently the sacco repeatedly transmits the xfifo-data via pin txd. the cyclical transmission continues until the command (cmdr:xres) is executed or the bit xrep is reset. the inter frame timefill pattern is issued afterwards. when resetting xrep, data transmission is stopped after the next xfifo-cycle is completed, the xres-command terminates data transmission immediately. note: bit mode:cft must be set to 0. continuous transmission (dma-mode only) if data transfer from system memory to the sacco is done by dma (dma bit in xbch set), the number of bytes to be transmitted is usually defined via the transmit byte count registers xbch, xbcl. setting the transmit continuously bit (xc) in xbch, however, the byte count value is ignored and the dma-interface of the sacco will continuously request for transmit data any time 32 bytes can be stored in the xfifo. this feature can be used e.g. to ? continuously transmit voice or data onto a pcm-highway (clock mode 2, ext. transp. mode) ? transmit frames exceeding the byte count programmable in xbch, xbcl (> 4095 bytes). note: if the xc-bit is reset during continuous transmission, the transmit byte count becomes valid again, and the sacco will request the amount of dma-transfers programmed in xbc11xbc0. otherwise the continuous transmission is stopped when a data underrun condition occurs in the xfifo, i.e. the dma-controller does not transfer further data to the sacco. in this case an abort sequence (min. 7 1s) followed by the inter frame timefill pattern is transmitted (no crc-word is appended). receive length check the sacco offers the possibility to supervise the maximum length of received frames and to terminate data reception in case this length is exceeded. this feature is enabled by setting the rc- (receive check) bit in rlcr and programming the maximum frame length via bits rl6rl0. peb 20560 functional block description semiconductor group 2-28 1997-11-01 according to the value written to rl6rl0, the maximum receive length can be adjusted in multiples of 32-byte blocks as follows: max. frame length = (rl + 1) 32. all frames exceeding this length are treated as if they have been aborted from the opposite station, i.e. the cpu is informed via a C rme-interrupt, and the C rab-bit in rsta register is set (clock mode 0 - 2) to distinguish between frames really aborted from the opposite station, the receive byte count (readable from registers rbch, rbcl) exceeds the maximum receive length (via rl6rl0) by one or two bytes in this case. 2.1.2.4.6 serial interface clock modes the sacco uses a single clock for transmit and receive direction. three different clock modes are provided to adapt the serial interface to different requirements. clock mode 0 serial data is transferred on rxd/txd, an external generated clock (double or single data rate) is forwarded via pin hdc. clock mode 1 serial data is transferred on rxd/txd, an external generated clock (double or single data rate) is forwarded via pin hdc. additionally a receive/transmit strobe provided on pin hfs is evaluated. clock mode 2 this operation mode has been designed for applications in time-slot oriented pcm- systems. the sacco receives and transmits only during a certain time-slot of programmable width (1256 bits) and location with respect to a frame synchronization signal, which must be delivered via pin hfs. the position of the time-slot can be determined applying the formula in figure 2-18 . tsn defines the number of 8 bit time-slots between the start of the frame (hfs edge) and the beginning of the time-slot for the hdlc channel. the values for tsn are written to the registers tsar:7 ? 2 and tsn:7 ? 2. cs additionally a clock shift of 0 ? 7 bits can be defined using register bits tsar:rsc21, tsax:xcs2 ? 1 and ccr2:xcs0, ccr2:rcs0. together tsn and cs provide 9 bits to determine the location of the time-slot for the hdlc channel. peb 20560 functional block description semiconductor group 2-29 1997-11-01 one of up to 64 time-slots can be programmed independently for receive and transmit direction via the registers tsar and tsax. according to the value programmed via those bits, the receive/transmit window (time-slot) starts with a delay of 1 (minimum delay) up to 512 clock periods following the frame synchronization signal and is active during the number of clock periods programmed via rccr, xccr (number of bits to be received/transmitted within a time-slot) as shown in figure 2-18 . figure 2-18 location of time-slots note: in extended transparent mode the width of the time-slot has to be n 8 bit. clock mode 3 in clock mode 3 sacco-a is multiplexed among multiple subscribers under the control of the d-channel arbiter. it must be used only in combination with transparent mode 0. serial data is transferred on (received from) the d-channels of the epic-1 iom-2 interfaces. the data clock is derived from dcl. the d-channel arbiter generates the receive and transmit strobes. when bit ccr2:txde is set, the transmitted d-channel data can additionally be monitored on pin txda delayed by 1 bit. the timing is identical to clock mode 1 assuming a transmit strobe during the transmission of the third and fourth bit following the rising fsc-edge. itd05839 time-slot number tsn (6 bits) clock shift cs (3 bits) 9 bits xcs 2 rcs 0 rcs 1 rcs 2 xcs 1 xcs 0 ccr 2 tsnr tsnx tsar tsax time-slot hfs hdc width rccr, xccr (1...256 clocks) (1...512 clocks) delay 1+tsnx8+cs peb 20560 functional block description semiconductor group 2-30 1997-11-01 receive status byte in clock mode 3 in clock mode 3 the receive status byte is modified when it is copied into rfifo. it contains the following information: vfr valid frame. indicates whether the received frame is valid (1) or not (0 invalid). a frame is invalid when C its length is not an integer multiple of 8 bits (n 8 bits), e.g. 25 bit, C it is too short, depending on the selected operation mode (transparent mode 0: 2 bytes minimum), the frame was aborted from the transmitting station. rdo receive data overflow. a 1 indicates, that a rfifo-overflow has occurred within the actual frame. crc crc compare check. 0: crc check failed, received frame contains errors. 1: crc check o.k., received frame is error free. chad40 channel address 40. chad40 identifies on with iom-port/channel the corresponding frame was received: chad43: iom-port number (3 - 0) of elic ( 1 doc port number) chad20: iom-channel number (7 - 0) note: the contents of the receive status register is not changed. 2.1.2.4.7 serial port configuration the sacco supports different serial port configuration, enabling the use of the circuit in C point-to-point configurations C point-to-multi-point configurations C multi master configurations point-to-point configuration the sacco transmits frames without collision detection/resolution. (ccr1:sc1, sc0: 00) additionally the input cxd can be used as a clear to send strobe. transmission is inhibited by a 1 on the cxd-input. if cxd becomes 1 during the transmission of a frame, the frame is aborted and idle is transmitted. the cxd-pin is evaluated with the bit 7 bit 0 vfr rdo crc chad4 chad3 chad2 chad1 chad0 peb 20560 functional block description semiconductor group 2-31 1997-11-01 falling edge of hdc. when the clear to send function is not needed, cxd must be tied to v ss . bus configuration the sacco can perform a bus access procedure and collision detection. as a result, any number of hdlc-controllers can be assigned to one physical channel, where they perform statistical multiplexing. collisions are detected by automatic comparison of each transmitted bit with the bit received via the cxd input. for this purpose a logical and of the bits transmitted by parallel controllers is formed and connected to the input cxd. this may be implemented most simply by defining the output line to be open drain. consequently the logical and of the outputs is formed by simply tying them together (wired or). the result is returned to the cxd-input of all parallel circuits. when a mismatch between a transmitted bit and the bit on cxd is detected, the sacco-stops sending further data and idle is transmitted. as soon as it detects the transmit bus to be idle again, the controller automatically attempts to re-transmit its frame. by definition, the bus is assumed idle when x consecutive ones are detected in the transmit channel. normally x is equal to 8. an automatic priority adjustment is implemented in the multi master mode. thus, when a complete frame is successfully transmitted, x is increased to 10, and its value is restored to 8 when 10 '1's are detected on the bus (cxd). furthermore, transmission of new frames may be started by the controller after the 10 th 1. this multi master, deterministic priority management ensures an equal right of access of every hdlc-controller to the transmission medium, thereby avoiding blocking situations. compared to the version 1.2 the version 1.3 provides new features: push-pull operation may be selected in bus configuration (up to version 1.2 only open drain): ? when active txda / txdb outputs serial data in push-pull-mode. ? when inactive (interframe or inactive time-slots) txda / txdb outputs 1. note: when bus configuration with direct connection of multiple elics is used open drain option is still recommended. the push-pull option with bus configuration can only be used if an external tri-state buffer is placed between txda / txdb and the bus. due to the delay of tsca / tscb in this mode (see description of bits soc(0:1) in register ccr2 ( chapter 5.1.1.6.9 ) these signals cannot directly be used to enable this buffer. peb 20560 functional block description semiconductor group 2-32 1997-11-01 timing mode when the multi master configuration has been selected, the sacco provides two timing modes, differing in the period between sending data and evaluating the transmitted data for collision detection. C timing mode 1 (ccr1:sc1, sc0 = 01) data is output with the rising edge of the transmit clock via txd and evaluated 1/2 clock period later with the falling clock edge at the cxd pin. C timing mode 2 (ccr1:sc1, sc0 = 11) data is output with the falling clock edge and evaluated with the next falling clock edge. thus a complete clock period is available during data output and their evaluation. 2.1.2.4.8 test mode to provide support for fast and efficient testing, the sacco can be operated in the test mode by setting the tlp-bit in the mode-register. the serial input and output pins (txd, rxd) are connected generating a local loop back. as a result, the user can perform a self-test of the sacco. transmit lines txda/b are also active in this case, receive inputs rxda/b are deactivated. 2.1.2.5 d-channel arbiter the d-channel arbiter facilitates the simultaneous serving of multiple d-channels with one hdlc-controller (sacco-a) allowing a full duplex signaling protocol (e.g. lapd). it builds the interface between the serial input/output of sacco-channel a and the time-slot oriented d-channels on the epic-1 iom-2 interface. the sacco-operation mode transparent mode 0 has to be selected when using the arbiter. it is only possible to operate the d-channel arbiter with framing control modes 3, 6 and 7, (refer to register epic-1.cmd2:fc(2:0)). the arbiter consists of three sub blocks: ? arbiter state machine (asm): selects one subscriber for upstream d-channel assignment ? control channel master (ccm): issues the d-channel available information from the arbiter in the control channel ? transmit channel selector (tchs): selects one or a group of subscribers for d-channel assignment peb 20560 functional block description semiconductor group 2-33 1997-11-01 figure 2-19 d-channel arbiter 2.1.2.5.1 upstream direction in upstream direction the arbiter assigns the receive channel of sacco-a to one subscriber terminal. it uses an unidirectional control channel to indicate the terminals whether their d-channels are available or blocked. the control channel is implemented using different existing channel structures to close the transmission path between the line card hdlc-controller and the hdlc-controller in the subscriber terminal. on the line card, the control channel is either integrated in the c/i-channel or transmitted in the mr-bit depending on a programming of bit amo:cchh (octat-p ? c/i channel, ibc ? mr-bit). its05840 transmit channel selector tchs mux mux control channel master ccm arbiter state machine asm sacco-a transmit channel sacco-a receive channel serial data out transmit strobe receive strobe serial data in port 0 port 1 port 2 port 3 down stream stream up port 3 port 2 port 1 port 0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 iom -2 channels control data d-channel arbiter r peb 20560 functional block description semiconductor group 2-34 1997-11-01 arbiter state machine the d-channel assignment is performed by the arbiter state machine (asm), implementing the following functionality. (0) after reset or when sacco-a clock mode is not 3 the asm is in the state suspended . the user can initialize the arbiter and select the appropriate sacco clock mode (mode 3). (1) when the receiver of sacco-a is reset and clock mode 3 is selected the asm enters the state full selection . in this state all d-channels enabled in the d-channel enable registers (dce) are monitored. (2) upon the detection of the first 0 the asm enters the state expect frame . when simultaneously 0s are detected on different iom-2 channels, the lowest channels number is selected. channel and port address of the related subscriber are latched in arbiter state register (astate), the receive strobe for sacco-a is generated and the dce-values are latched into a set of slave registers (dces). additionally a suspend counter is loaded with the value stored in register scv. the counter is decremented after every received byte (4 iom-frames). (3) when the counter underflows before the state expect frame was left, the corresponding d-channel is considered to produce permanent bit errors (typical pattern: 111011101011). the asm emits an interrupt, disables the receive strobe and enters the state suspended again. the user can determine the affected channel by reading register astate. in order to reactivate the asm the user has to reset the sacco-a receiver. (4) when seven consecutive 1s are detected in the state expect frame before the suspend counter underflows the asm changes to the state limited selection . the previously detected 0 is considered a single bit error (typical pattern: 11111101111111111). the receive strobe is turned off and the dces-bit related to the corresponding d-channel is reset, i.e. the subscriber is temporarily excluded of the priority list. (5) when sacco-a indicates the recognition of a frame (frame indication after receiving 3 bytes incl. the flag) before the suspend counter underflows the asm enters the state receive frame . (6) the asm-state changes from receive frame to limited selection when sacco-a indicates end of frame. the receive strobe is turned off and the dces-bit related to the corresponding d-channel is reset. the asm again monitors the d-channels but limited to the group enabled in the slave registers dces anded with dce. the and function guarantees, that the user controlled disabling of a subscriber has immediate effect. (7) when the asm detects a 0 on the serial input line it enters the state expect frame . channel and port address of the related subscriber are latched in the arbiter state register (astate), the receive strobe for sacco-a is generated and peb 20560 functional block description semiconductor group 2-35 1997-11-01 the suspend counter is loaded with the value stored in register scv. the counter is decremented after every received byte. when simultaneously 0s are detected on different iom-2 channels, the lowest channel is selected. (8) when the asm does not detect any 0 on the remaining serial input lines during n iom-frames (n is programmed in the register amo) it re-enters the state full selection . the list of monitored d-channels is then increased to the group selected in the user programmable dce-registers. in order to avoid arbiter locking n has to be greater than the value described in chapter 2.1.2.5.3 or must be set to 0. (9) if n is set to 0, then the state limited selection is skipped. the described combination of dce and dces implements a priority scheme guaranteeing that (almost) simultaneous requesting subscribers are served sequentially before one is selected a second time. the current asm-state is accessible in astate7:5. peb 20560 functional block description semiconductor group 2-36 1997-11-01 figure 2-20 arbiter state machine (asm) itd05841 sus- pended strobe on latch ch-address restart suspend counter latch dces registers * * * * frame expect full selection receive frame limited selection * * * counter restart suspend latch ch-address strobe on 2 "0" strobe off reset dces[i] * * * * interrupt strobe off * * reset dces[i] strobe off "0" 7 4 6 3 5 1 0 8 sacco_a : frame end sacco_a : frame indication suspend counter underflow elic reset or sacco_a : clock mode < >3 sacco_a : receiver reset and clock mode = 3 n iom frames without "0" 7* 1" " r r am0 : fcc4...0=0 9 sacco_a : frame end strobe off reset dces[i] * * peb 20560 functional block description semiconductor group 2-37 1997-11-01 control channel master the control channel master (ccm) issues the d-channel available information in the control channel as shown in table 2-10 . if a d-channel is not enabled by the arbiter, the control channel passes the status, stored in the epic-1 control memory (c/i, mr). for correct operation of the arbiter this status bit has to contain the blocked information for all d-channels under control of the arbiter. if the asm is in the state suspended the arbiter functionality depends on the status of the control channel master: the ccm is enabled if amo:cchm = 1. all subscribers will be sent the available/blocked information (c/i or mr) as programmed in the control memory. however, the control memory should be programmed as blocked. the ccm is disabled if amo:cchm = 0. all in the dce-registers enabled subscribers (dce = 1) will be sent the information available (which has a higher priority than the blocked information from epic-1). if the asm is in the state full selection all d-channels are marked to be available which are enabled in the user programmable dce-registers. when the user reprograms a dce-register this has an immediate effect, i.e. a currently transmitting subscriber can be forced to abort its message. if the asm is in the state limited selection the subscribers which are currently enabled in dce and dces get the information available; they can access the d-channel. the dce/dces and ing is performed in order to allow an immediate disabling of individual subscribers. in the state expect frame and receive frame all channels except one (addressed by astate4:0) have blocked d-channels. the disabling of the currently addressed d-channel in dce has an immediate effect; the transmitter (hdlc-controller in the subscriber terminal) is forced to abort the current frame. depending on the programming of amo:cchh the available/blocked information is coded in the c/i-channel or in the mr-bit. the cchm is activated independently of the sacco-clock mode by programming amo:cchm. even when the asm is disabled (clock mode not 3) the cchm can be activated. in this case the content of the dce-registers defines which d-channels are enabled. table 2-10 control channel implementation cchh control via available blocked 1mr10 0 c/i x0xx x1xx peb 20560 functional block description semiconductor group 2-38 1997-11-01 when a d-channel is enabled in the dce-register and available, the control channel master takes priority over the c/i- (mr) values stored in the epic-1 control memory and writes out either mr = 1 or c/i = x0xx. when a d-channel is enabled but blocked, the control channel master simply passes the c/i- (mr) values which are stored in the epic-1 control memory. these values should have been programmed as mr = 0 or c/i = x1xxx. when a d-channel is disabled in the dce-register the control channel master simply passes the c/i- (mr) values which are stored in the epic-1 control memory. this gives the user the possibility to exclude a d-channel from the arbitration but still decide whether the excluded channel is available or blocked. overview of different conditions for control channel handling/information sent to subscribers: 2.1.2.5.2 downstream direction in downstream direction no channel arbitration is necessary because the sequentiality of the transmitted frames is guaranteed. in order to define iom-channel and port number to be used for a transmission, the transmit channel selector (tchs) provides a transmit address register (xdc) which the user has to write before a transmit command (xtf) is executed. depending on the programming of the xdc-register the frame is transmitted in the specified d-channel or send as broadcast message to the broadcast group defined in the registers bcg1-4. due to the continuous frame transmission feature of the sacco, the full 16-kbit/s bandwidth of the d-channel can be utilized, even when addressing different subscribers. note: the broadcast group must not be changed during the transmission of a frame table 2-11 clock mode 3 x x asm state not suspended suspended x cchm 1 = enabled 1 = enabled 0 = disabled subscriber in dces enabled disabled enabled disabled enabled disabled information sent to subscribers = available or blocked according to the d-channel arbiter state (ccm) content of the epic-1 control memory- (c/i or mr) content of the epic-1 control memory- (c/i or mr) content of the epic-1 control memory- (c/i or mr) available! content of the epic-1 control memory- (c/i or mr) peb 20560 functional block description semiconductor group 2-39 1997-11-01 2.1.2.5.3 control channel delay depending on the selected system configuration different delays between the activation of the control channel and the corresponding d-channel response occur. beware of arbiter locking! in the state limited selection, the d-channel arbiter sends the blocked information to the terminal from which the last hdlc-frame was received. since the blocked information reaches the terminal with several iom-frames delay t ccdd (e.g. after 5 125 m s) the terminal may already have started sending a second hdlc-frame. on reception of the blocked information the terminal immediately aborts this frame. since the abort sequence of the second frame reaches the elic with several frames delay t dcdu , the full selection counter value must be set so that the d-channel arbiter re-enters the state full selection only after the abort sequence of the second frame has reached the elic. if the d-channel arbiter re-enters the full selection state (in which it again sends an available information to the terminal) before the abort sequence has reached the elic, it would mistake a 0 of the second frame as the start of a new frame. when the delayed abort sequence arrives at the elic, the d-channel arbiter would then switch back to the state limited selection and re-block the terminal. thus the d-channel arbiter would toggle between sending available and blocked information to the terminal, forever aborting the terminals frame. the arbiter would have locked. table 2-12 control channel delay examples number of frames (= 125 m s) system configuration circuit chain blocked ? available available ? blocked min. max. min. max. u pn line card - - u pn phone elic + octat-p + isac-p te 4848 u pn line card - - s 0 adapter - - s 0 phone elic + octat-p + isac-p te + sbcx + isac-s 91359 u pn line card - - u pn adapter - - u pn phone elic + octat-p + isac-p te + isac-p te + isac-p te 913913 s 0 line card - s 0 phone elic + quat-s + isac-s te 4848 peb 20560 functional block description semiconductor group 2-40 1997-11-01 in order to avoid such a locking situation the time t dfs min. (value in the amo-register) has to be greater then the maximum delay t ccdd (for the case available ? blocked) plus the delay t dcdu . C for the quat-s a value of 0 is recommended for the suspend counter (register scv). for the octat-p it is recommended to programscv = 1 in the case of 2 terminals scv = 0 if one terminal is used. see the following diagram: figure 2-21 2.1.2.5.4 d-channel arbiter co-operating with quat-s circuits when d-channel multiplexing is used on a s 0 -bus line card, only the transmit channel selector of the arbiter is used. the arbiter state machine can be disabled because the quat-s offers a self arbitration mechanism between several s 0 -buses. this feature is implemented by building a wired or connection between the different e-channels. as a result, the arbitration function "blocked" passes dfs min. = delay for switch to "full selection" (value in amo) = min. delay for not locking condition i = d-channel delay upstream = control channel delay downstream note: if the full selection counter value (amo : fcc4...0) is not changed from its reset value 00 , then the d-channel arbiter (asm) skips the state "limited selection". d-channel arbiter states fs = full selection ls = limited selection ef = expect frame rf = receive frame rf t ccdd dfs dcdu dfs t t t min. ls dfs t t fs t ef + rf h fs + ef ls dfs itd05842 abort ccdd "available" control channel from terminal at the arbiter hdlc frame dcdu start t end 1. frame ccdd t t 2. frame start 2. frame t dcdu start ccdd t ccdd t abort peb 20560 functional block description semiconductor group 2-41 1997-11-01 does not add additional delays. this means that the priority management on the s 0 -bus (two classes) still may be used, allowing the mixture of signaling and packet data. nevertheless, it still can make sense to use the elic arbiter in this configuration. the advantage of using the arbiter is, that if one terminal fails the others will not be blocked. 2.2 sidec the sidec is a 4-channel signaling controller containing slightly modified sacco modules and a control logic for drdy handling (stop/go signal from quat-s). figure 2-22 sidec block diagram depending on the drdy signal from quat-s (in lt-t mode) the sidecn sends data in the programmed time-slot or waits for a go signal, figure 2-22 and figure 2-23 . clk sync sidec 0 ff txclk0 cts0 ff cts3 txclk3 sync sidec 3 clk sidec r iom -mux elic r -0 txd0 tsc0 rxd0 rxd3 txd3 tsc3 pdc0 fsc0 r quat -s drdy doc ff = flip flop itb10077 peb 20560 functional block description semiconductor group 2-42 1997-11-01 figure 2-23 sidec signals the drdy signal is latched internally using a timeslot indication signal txclkx and switches the transmission on/off via the ctsx pins. a stop forces the affected channel to abort the hdlc frame; upon a go the affected channel restarts the frame. 2.3 multiplexers as the doc contains two independent switches and eight different hdlc controllers, multiple programmable (multimode) multiplexers are implemented ( figure 2-24 ): ? an iom-ports multiplexer ? a pcm-ports multiplexer ? iom and pcm signaling multiplexers ? an elic1-port multiplexer itd10078 dd dd signaling data to co r iom -2 iom r iom r channel 0 channel 3 "go" "stop" drdy ~ txclk0 ~ ~ txclk3 ~ ~ inactive active cts0 ~ ~ inactive txd0 active ~ ~ ~ ~ inactive cts3 active inactive txd3 active ~ ~ ~ peb 20560 functional block description semiconductor group 2-43 1997-11-01 all multiplexers can be programmed to different modes of operation. figure 2-24 principle block diagram of iom and pcm multiplexers; mode 0-0-0-0-1 note: mode 0-0-0-0-1 means: the iom-ports multiplexer is in mode 0 the elic cfi ports are in mode 0 the elic pcm ports are in mode 0 the pcm-ports multiplexer is in mode 0 the elic1-ports multiplexer is in mode 1 the meaning of the circles within the signaling multiplexers is explained in figure 2-25 . itb10079 sacco-a0 elic r -0 sacco-b0 0 1 2 3 0 1 2 3 mode 0 mode 0 sacco-a1 sacco-b1 33 elic 2 1 0 -1 r 2 1 0 mode 0 signaling sidec = 4 x hdlc dsp mode 0 signaling ports cfi pcm ports 3 2 1 0 pcm 4 x 32 ts = 128 ts 4 signaling (+4 via i/o port) 2 3 2 1 0 r iom -2 interfaces 7 6 5 4 sacco-b1 4 x 32 ts as local network controller with all lines (dma...) drdy elic -1 ports r multiplexer in mode 1 - mux r iom pcm - mux doc highways -s elic r peb 20560 functional block description semiconductor group 2-44 1997-11-01 any one of the six hdlc controllers may be assigned to elic0 port1 (as an example) in one of the 3 following ways only: ? the hdlc transmits in data upstream direction via du01 line or ? the hdlc transmits in data downstream direction via dd01 line or ? the hdlc is not connected to elic0 port1 at all. . figure 2-25 modes of hdlc connection to iom ? -2 interfaces within the signaling mux the meaning of the dark circles within the ports multiplexers is similar. elic1 cfi ports may be assigned as follows: ? all dd lines of elic1 are connected to dd lines of elic0 (dd10 with dd00, ) and all du lines of elic1 are connected to du lines of elic0 (du10 with du00, ) ? the elic1 is not connected with elic0 at all. the dsp is always connected with one port to elic0 port0 and with its second port to elic1 port1. see also figure 2-31 . both elics run with the same data and sync clocks. its10080 sacco-a0 sacco-b0 3 2 1 0 elic r -0 r -2 iom 6 x hdlc dd01 du01 hdlc rxd txd a) iom -2 r port 1 iom b) hdlc rxd txd port 1 -2 r du01 dd01 elic -0 r hdlc rxd iom c) -2 r txd dd01 du01 port 1 elic -0 r elic r -0 peb 20560 functional block description semiconductor group 2-45 1997-11-01 2.3.1 iom ? - and pcm-ports multiplexers 2.3.1.1 iom ? multiplexer for iom ? -2 ports (cfi interfaces of epic) the iom multiplexer connects the 8 iom-2 ports to the two integrated elics. the iom-mux can be programmed to one of 2 different modes: mode 0 ? elic0 and elic1 are connected together: dd00 with dd10, du00 with du10, mode 1 ? all elic0 lines (iom) reach doc pins (iom-2 ports 0 to 3) ? elic1 lines reach elic1-port multiplexer and are not connected to any elic0 line. (state after doc reset) figure 2-26 iom ? ports multiplexer in mode 1 and elic ? -1-ports multiplexer in mode 0 its10081 sacco-b0 3 2 1 0 elic r -0 r -interfaces iom 3 2 1 0 signaling mode 1 mode 0 elic sacco-b1 3 2 1 0 -1 r dsp sidec = 4 x hdlc 7 6 5 4 2 x 32 ts or elic -1-port r multiplexer mode 0 -mux iom r cfi ports 1 x 64 ts peb 20560 functional block description semiconductor group 2-46 1997-11-01 2.3.1.2 pcm-ports multiplexer for pcm highways the pcm multiplexer connects the 4 pcm ports of the doc to the two integrated elics. the pcm-mux can be programmed to one of 2 different modes: mode 0 ? elic0 and elic1 are connected together: txd00 with txd10, rxd00 with rxd10, figure 2-24 (state after doc reset) mode 1 ? only the ports 0 and 2 of both elics are connected to doc pins, figure 2-27 figure 2-27 pcm-ports multiplexer in mode 1 the txd output data lines at the doc have tri-state capability so that the doc may be connected in parallel with further devices at the pcm interface. additional tri-state control lines (tsc ) indicate valid/invalid time-slots on the pcm interface. they can be used as control signals for external drivers. the rxd inputs contain a protection logic limiting the input current to 2.3 ma if the doc is without power supply. its10082 sacco-a0 elic r -0 sacco-b0 0 1 2 3 sacco-a1 sacco-b1 3 elic -1 r 2 1 0 mode 1 signaling pcm ports 3 2 1 0 pcm signaling elic pcm - mux highways -s r peb 20560 functional block description semiconductor group 2-47 1997-11-01 2.3.2 multiplexers for signaling controllers all 8 integrated hdlc controllers can be used for d-channel signaling. 6 hdlc controllers can also be used for b-channel access. the following configurations are programmable: 2.3.2.1 sacco-a0 and sacco-a1 both sacco-a are dedicated to work with the d-channel arbiter only. they must always operate in transparent mode 0. for more details please refer to elic, peb 20550, users manual 1.96. neither sacco-a are connected to any doc pin. 2.3.2.2 sacco-b0 the serial interface can be assigned by the pcm signaling multiplexer to 3 different applications: 1. to any time-slot on the iom-2 interface port 0 to 3 in dd or du direction 2. to the four pcm highways in dd or du direction 3. as a stand-alone controller refer to figure 2-24 . 1) in clock mode 0 are only the first 64 time-slots accessable. table 2-13 controllers comm. channels connection max. data rate to via sacco-a0 d iom-2 d-ch. arbiter0 16 kbit/s sacco-a1 d iom-2 d-ch. arbiter1 16 kbit/s sacco-b0 d, b, general iom-2, pcm or ext. multiplexers 8.192 mbit/s 1) sacco-b1 d, b, general iom-2, pcm or ext. multiplexers 8.192 mbit/s 1) sidec d and b iom-2 multiplexer 4 64 kbit/s peb 20560 functional block description semiconductor group 2-48 1997-11-01 figure 2-28 sacco-b0 multiplexers the sacco-b0 can also be used as a stand-alone hdlc controller. the i/o port can be programmed to provide all additional support lines (dma interface). different clock sources for transmit and receive data (dclk) and for frame clock (sync) can be selected by the user. the input signal cxdb0 enables/inhibits the hdlc controller assigned to the s/t transceiver (i.e. quat-s in lt-t mode); refer to figure 2-29 . its10083 txdb0 tscb0 rxdb0 cxdb0 port0/drqtb0 port1/drqrb0 port2/dackb0 port3/hfsb0 dclk multiplexer sacco-b0 pdc2 pdc8 pdc4 dcl0 sacco-b0 sync multiplexer hfsb0 pfs fsc hdc hfs txd tsc rxd cxdb0 drqtb0 drqrb0 dackb0 sacco-b0 tcs txd rxd rxd tcs txd -mux iom r pcm-mux doc 4 multiplexer i/o port i/o port signaling peb 20560 functional block description semiconductor group 2-49 1997-11-01 figure 2-29 quat-s with sacco-b for single-channel lt-t application 2.3.2.3 sacco-b1 the serial interface can be assigned by the pcm signaling multiplexer to 3 different applications: 1. to any time-slot on the iom-2 interface port 0 to 3 in dd or du directions 2. to the four pcm highways in dd or du directions 3. as a stand alone controller refer to figure 2-24 . its05461 d-channel sacco-a sacco-b elic pcm c m quat-s 2084 peb iom cfi d-ch. txd rxd lt-s lt-t drdy "0" "1" = = go stop t x 1 nt + ed d arbiter -2 r doc peb 20560 functional block description semiconductor group 2-50 1997-11-01 figure 2-30 sacco-b1 multiplexers the sacco-b1 can be used as a stand-alone hdlc controller with dma control lines if only 4 iom-2 interfaces are used. the elic1 ports multiplexer must be in mode 1 or 2, figure 2-30 . the transmit and receive data clocks and the sync clock are selectable. 2.3.2.4 sidec the four serial interfaces of the sidec can be assigned to: ? any d-channel or b-channel of the four iom-2 interfaces of elic0 via the iom-signaling multiplexer ? individually in data downstream or in data upstream direction. sidec is connected to fsc and dcl (of elic0). see also figure 2-22 . its10084 multiplexer pcm-signaling txd tcs rxd rxd multiplexer tcs txd r iom -signaling 8 -ports multiplexer iom r elic -1 r fsc pfs hfsb1 sacco-b1 sync multiplexer sacco-b1 dclk multiplexer pdc2 pdc4 pdc8 dcl hdc txd tsc rxd sacco-b1 hfs drqrb1 cxdb1 drqtb1 dackb1 doc elic -1 ports r multiplexer dd4/txdb1 dd5/tscb1 du4/rxdb1 du6/cxdb1 dd6/drqtb1 dd7/drqrb1 du7/dackb1 du5/hfsb1 8 peb 20560 functional block description semiconductor group 2-51 1997-11-01 2.3.3 elic1-ports multiplexer the elic1-ports multiplexer can operate in three different modes: mode 0 the elic1 is connected to doc pins; iom-2 ports 4 to 7 (after reset) C figure 2-26 mode 1 sacco-b1 is connected to doc pins; to iom-2 ports 4 to 7 thus the sacco-b1 can be used as a stand-alone controller C figure 2-30 . mode 2 port 0 of elic1 is connected to doc pins (iom-2 port 4) iom-2 ports 5 to 7 are connected with sacco-b1. in this mode, elic1 can be used in epic cfi mode 2 (8.192 mbit/s on port 0) and the sacco-b1 can be used with all lines without restrictions. the txd, rxd and tsc lines can be assigned to any iom-2 port (0 to 3) or as described above. note: after reset, the multiplexers around elics ( figure 2-24 ) are in the following states: table 2-14 iom-ports-multiplexer mode 1. iom-signaling-multiplexer no one signaling controller is connected to iom-2. pcm-ports-multiplexer mode 0. pcm-signaling-multiplexer no one signaling controller is connected to pcm highways elic1-ports multiplexer mode 0 peb 20560 functional block description semiconductor group 2-52 1997-11-01 2.3.4 iom ? -multiplexer for dsp connection to epics the dsp is connected to the elic0, ports 0, and to the elic1, port1, via a pcm-dsp interface unit (pediu). figure 2-31 shows the iom-port multiplexer in mode 1. figure 2-31 pediu connection to the elics ? the dsp can be connected to both elics or to elic0 only (via in0 and out0). ? elic0 and elic1 can be programmed for fsc and dcl be input or output clocks, depending on the system requirements. note: if fsc/dcl are outputs of the elic0/1, only the outputs of elic0 drive the port pins fsc/dcl of the doc. the clock outputs of elic1 are not connected in this case. ? pediu data clock = dcl0 or pdc4 or pdc8 pdc8 requires a dsp clock of 40 mhz. ? pediu frame sync clock = fsc0 or pfs its10085 fsc0 elic -0 r dcl0 dd00 tsc00 du00 elic fsc1 du11 tsc11 dd11 dcl1 r -1 dsp pfs pdc4 or pdc8 gen. clock pfs pdc2 pdc4 pdc8 in0 in1 tsc clks out0 out1 pediu mode r iom -mux r iom -interfaces fsc dcl dd0 du0 dd du cfi peb 20560 functional block description semiconductor group 2-53 1997-11-01 2.3.5 pcm/iom mux registers description 2.3.5.1 pcm/iom mux mode register (mmode) address: 380 h m p interface mode: read/write reset value: 01 h note: bits 7 4 are unused, and are read as 0. this register defines muxes modes: ? iom mux: mode0, mode1 ? pcm mux: mode0, mode1 ? elic1 mux: mode0, mode1, mode2 el1m10 - elic1 mux mode if im = 1 00: elic1 mux mode0: elic1 is connected to iom-2 ports 4-7 01: elic1 mux mode1: sacco-b1 is connected to iom-2 ports 4-7 10: elic1 mux mode2: sacco-b1 is connected to iom-2 ports 5-7 elic1 port 0 is connected to iom-2 port 4 sacco-b1 txd and rxd are connected to one of iom-2 ports03. note: cxdb1 is internally tied to v ss in mode 0. pm - pcm mux mode 0: pcm mux mode0: elic0 and elic1 are connected together to pcm ports03 1: pcm mux mode1: elic0 pcm ports 0, 2 are connected to doc pcm ports 0, 2 elic1 pcm ports 0, 2 are connected to doc pcm ports 1, 3 im - iom mux mode 0: iom mux mode0: elic0 and elic1 are connected together to iom-2 ports03. elic1 is connected to elic1 port mux 1: iom mux mode1: elic0 is connected to iom ports03; elic1 is connected to elic1 mux note: for an overview please refer to workingsheets for multiplexers programming, chapter 9.2 bit 7 bit 0 0000 el1m1 el1m0 pm im peb 20560 functional block description semiconductor group 2-54 1997-11-01 2.3.5.2 cfi channel select 0 register (mcchsel0) address: 381 h m p interface mode: read/write reset value: 00 h this register selects the iom port that sidec0 and sidec1 will be connected to. cd1 : connect/disconnect sidec1 0: sidec1 is disconnected from iom signaling mux 1: sidec1 is connected to iom signaling mux dir1 : the direction of sidec1 connection 0: hdlc txd line connected to iom dd line hdlc rxd line connected to iom du line 1: hdlc txd line connected to iom du line hdlc rxd line connected to iom dd line pn1 10 : port number which sidec1 is connected to. 00: iom port: port0 01: iom port: port1 10: iom port: port2 11: iom port: port3 cd0 : connect/disconnect sidec0 0: sidec0 is disconnected from iom signaling mux 1: sidec0 is connected to iom signaling mux dir0 : the direction of sidec0 connection 0: hdlc txd line connected to iom dd line hdlc rxd line connected to iom du line 1: hdlc txd line connected to iom du line hdlc rxd line connected to iom dd line pn0 10 : port number which sidec0 is connected to. 00: iom port: port0 01: iom port: port1 10: iom port: port2 11: iom port: port3 bit 7 bit 0 cd1 dir1 pn11 pn10 cd0 dir0 pn01 pn00 peb 20560 functional block description semiconductor group 2-55 1997-11-01 2.3.5.3 cfi channel select 1 register (mcchsel1) address: 382 h m p interface mode: read/write reset value: 00 h this register selects the iom port that sidec2 and sidec3 will be connected to. cd3 : connect/disconnect sidec3 0: sidec3 is disconnected from iom signaling mux 1: sidec3 is connected to iom signaling mux dir3 : 1) the direction of sidec3 connection 0: hdlc txd line connected to iom dd line hdlc rxd line connected to iom du line 1: hdlc txd line connected to iom du line hdlc rxd line connected to iom dd line pn3 10 : 1) port number which sidec3 is connected to. 00: iom port: port0 01: iom port: port1 10: iom port: port2 11: iom port: port3 cd2 : connect/disconnect sidec2 0:sidec2 is disconnected from iom signaling mux 1:sidec2 is connected to iom signaling mux dir2 : 1) the direction of sidec2 connection 0: hdlc txd line connected to iom dd line hdlc rxd line connected to iom du line 1: hdlc txd line connected to iom du line hdlc rxd line connected to iom dd line pn2 10 : 1) port number which sidec2 is connected to. 00: iom port: port0 01: iom port: port1 10: iom port: port2 11: iom port: port3 note: 1) only valid if cdx=1 bit 7 bit 0 cd3 dir3 pn31 pn30 cd2 dir2 pn21 pn20 peb 20560 functional block description semiconductor group 2-56 1997-11-01 2.3.5.4 cfi channel select 2 register (mcchsel2) address: 383 h m p interface mode: read/write reset value: 00 h this register selects the iom ports that sacco-b0 and sacco-b1 will be connected to. icdb1 : connect/disconnect sacco-b1 from iom signaling mux 0: sacco-b1 is disconnected from iom signaling mux 1: sacco-b1 is connected to iom signaling mux idirb1 : 1) the direction of sacco-b1 connection to iom signaling mux 0: hdlc txd line connected to iom dd line hdlc rxd line connected to iom du line 1: hdlc txd line connected to iom du line hdlc rxd line connected to iom dd line ipnb1 10 : 1) iom port number which sacco-b1 is connected to. 00: iom port: port0 01: iom port: port1 10: iom port: port2 11: iom port: port3 icdb0 : connect/disconnect sacco-b0 from iom signaling mux 0: sacco-b0 is disconnected from iom signaling mux 1: sacco-b0 is connected to iom signaling mux idirb0 : 1) the direction of sacco-b0 connection to iom signaling mux 0: hdlc txd line connected to iom dd line hdlc rxd line connected to iom du line 1: hdlc txd line connected to iom du line hdlc rxd line connected to iom dd line ipnb0 10 : 1) iom port number which sacco-b0 is connected to. 00: iom port: port0 01: iom port: port1 10: iom port: port2 11: iom port: port3 note: 1) only valid if icbx=1 bit 7 bit 0 icdb1 idirb1 ipnb11 ipnb10 icdb0 idirb0 ipnb01 ipnb00 peb 20560 functional block description semiconductor group 2-57 1997-11-01 2.3.5.5 pcm channel select 0 register (mpchsel0) address: 384 h m p interface mode: read/write reset value: 00 h this register selects the pcm ports that sacco-b0 and sacco-b1 will be connected to. pcdb1 : connect/disconnect sacco-b1 from pcm signaling mux 0: sacco-b1 is disconnected from pcm signaling mux 1: sacco-b1 is connected to pcm signaling mux pdirb1 : 1) the direction of sacco-b1 connection to pcm signaling mux 0: hdlc txd line connected to pcm txd line hdlc rxd line connected to pcm rxd line 1: hdlc txd line connected to pcm rxd line hdlc rxd line connected to pcm txd line ppnb1 10 : 1) pcm port number which sacco-b1 is connected to. 00: pcm port: port0 01: pcm port: port1 10: pcm port: port2 11: pcm port: port3 pcdb0: connect/disconnect sacco-b0 from pcm signaling mux 0: sacco-b0 is disconnected from pcm signaling mux 1: sacco-b0 is connected to pcm signaling mux pdirb0 : 1) the direction of sacco-b0 connection to pcm signaling mux 0: hdlc txd line connected to pcm txd line hdlc rxd line connected to pcm rxd line 1: hdlc txd line connected to pcm rxd line hdlc rxd line connected to pcm txd line ppnb0 10 : 1) pcm port number which sacco-b0 is connected to. 00: pcm port: port0 01: pcm port: port1 10: pcm port: port2 11: pcm port: port3 note: 1) only valid if pcdbx=1 bit 7 bit 0 pcdb1 pdirb1 ppnb11 ppnb10 pcdb0 pdirb0 ppnb01 ppnb00 peb 20560 functional block description semiconductor group 2-58 1997-11-01 2.4 channel indication logic (chi) an output signal (chi), as one additional line to the iom-2 interface, indicates when the fourth byte (byte 3) of each subframe comes. this byte carries 2 d-bits, 4 c/i-bits, mr and mx-bits or 6 c/i- and 2 m-bits in every iom-2 subframe. ? chi signal is programmable ? the chi signal may be activated or masked during the fourth byte of each subframe ? four 8 bits registers control the chi line ? every bit in the chi control register controls one subframe in iom-2 frame ? after reset chi is masked until control register programmed. cfi mode 0: 32 ts with 8 subframes 8 bits in one 8-bit register dcl = 2 x or 1 x data rate cfi mode 1: 64 ts with 16 subframes 16 bits in two 8-bit registers dcl = 1 x data rate cfi mode 2: 128 ts with 32 subframes 32 bits in four 8-bit registers dcl = 1 x data rate. figure 2-32 chi signal 2.4.1 chi configuration register (vmodr) address 323 h reset value 00 h chia - flag for chi logic activation (0-chi logic is inactive/1-chi logic is active) bit76543210 vmodr unused unused unused unused unused chia mod1 mod0 itd10086 01234567 0123 r iom -2 line-card mode 2.048 mbit/s iom r 8 channels 8888 mon b2 b1 211 4 d c/i mr mx chi peb 20560 functional block description semiconductor group 2-59 1997-11-01 mod1 - mod0 00 32 ts with 8 subchannels (single data rate), vdtr0 register is used as data register for chi logic programming. used when data frequency and data rate is 2.048 mhz 01 64 ts with 16 subchannels, vdtr0 & vdtr1 registers are used for chi logic programming. used when data frequency and data rate is 4.096 mhz 11 32 ts with 8 subchannels (double data rate), vdtr0 register is used as data register for chi logic programming. used when data frequency is 4.096 mhz and data rate 2.048 mhz 2.4.2 chi control registers (vdatr0:vdatr3) reset value: unchanged upon chip reset m p interface mode: read/write address: 324 h address: 325 h address: 326 h address: 327 h ctrln control bit for subframe n in iom-2 frame: 0 subframe is masked 1 subframe is enabled bit 76543210 vdatr0 ctrl7 ctrl6 ctrl5 ctrl4 ctrl3 ctrl2 ctrl1 ctrl0 bit 76543210 vdatr1 ctrl15 ctrl14 ctrl13 ctrl12 ctrl11 ctrl10 ctrl9 ctrl8 bit 76543210 vdatr2 ctrl23 ctrl22 ctrl21 ctrl20 ctrl19 ctrl18 ctrl17 ctrl16 bit 76543210 vdatr3 ctrl31 ctrl30 ctrl29 ctrl28 ctrl27 ctrl26 ctrl25 ctrl24 peb 20560 functional block description semiconductor group 2-60 1997-11-01 2.5 fsc with delay (fscd) f rame s ynchronization cl ock with d elay, which indicates the 32nd time-slot start, related to the standard fsc. used for synchronization of layer-1 devices connected to the second half of an extended iom-2 interface with 64 time-slots; (i.e. two octat-p connected to one 4 mbit/s iom-2 port). the fscd depends on the work mode of the pediu (pcm dsp interface unit): pediu work mode 0/1: 32 ts with 8 subchannels. fscd is not used (constantly 0). pediu work mode 2/3: 64 ts with 16 subchannels. fscd indicates the start of time-slot 32. it is delayed by 62.5 m s relative to fsc. pediu work mode 4: 128 ts with 32 subchannels. fscd indicates the start of time-slot 32. it is delayed by 125/4 m s (31.25 m s). for more details about the pediu work modes, refer to section 2.8.2.1: pediu control register (ucr) two additional points should be emphasized about fscd: 1. fscd can be used only when fsc direction is configured as output. otherwise, if fsc direction is configured as input, fscd will stay in tri-state. for more details on configuring fsc direction, refer to sections 2.10 and 2.12.3.1 . when fsc is configured as output and the pediu work mode is 0 or 1, or when the pediu is in idle mode, fscd will be driven as constant 0. 2. fscd is designed to be sampled by external devices with dcl falling edge. the next figure ( figure 2-33 ) demonstrate the behavior of fscd, when the pediu works in mode 2, 3 or 4 and it is not in idle mode, and when fsc direction is output. : figure 2-33 fscd behavior for more details about using fscd, refer to applications, section 6 . dcl (output) (output) fscd ts 31 last bit 32 ts 1'st bit 2'nd bit 32 ts new delayed frame sampling itd09691 peb 20560 functional block description semiconductor group 2-61 1997-11-01 2.6 digital signal processor (dsp) based on the cooperation between dsp group (usa) and siemens a signal processing core with extensions (oak) will be integrated in the doc. oak features: ? up to 40 mhz / 40 mips ? 7 instruction groups with totally 72 instructions (including bit manipulation) ? two independent 16-bit data busses (x and y) each with demultiplexed address and data busses 2.6.1 dsp kernel block diagram the dsp kernel consists of four units: computation unit (cu), bit manipulation unit (bmu), data addressing arithmetic unit (daau) and program control unit (pcu) 2.6.2 dsp instruction set the integrated dsp (oak) executes the following instructions: ? 20 arithmetic and logical instructions: add, addl, addh, addv, sub, subl, subh, subv, or, and, xor, cmp, cmpv, moda, norm, divs, max, maxd, min and lim. ? 12 multiply instructions: mpy, mpysu, mac, macsu, macus, macuu, maa, maasu, msu, mpyi, sqr and sqra. ? 10 bit manipulation instructions: set, rst, chng, tst0, tst1, tstb, chfc, shfi, modb and exp. ? 10 move instructions: mov, movp, movd, movs, movsi, movr, push, pop, swap and banke. ? 3 loop instructions: rep, brep and break. ? 10 branch and call instructions: br, brr, call, callr, calla, ret, retd, reti, retid and rets. ? 7 control and miscellaneous instructions: nop, modr, eint, dint, trap, load and cntx. peb 20560 functional block description semiconductor group 2-62 1997-11-01 2.7 dsp control unit (dcu) 2.7.1 general the dcu is responsible for the following tasks: ? dsp address decoding ? control of external memories ? emulation support ? interrupt handling and test support ? data bus and program bus arbitration ? dsp run time statistics ? program write protection ? boot support 2.7.2 dsp address decoding the dcu decodes the dsp data address bus (dxap) and the dsp program address bus (ppap) for performing the following tasks: ? generating dsp memory mapped i/o read and write signals based upon decoding of the 8 msb lines of the data address bus. ? generating the circular buffer ram read and write controls. ? generating external program and data ram controls upon detection of their address. ? generating read signal for the internal program rom. 1) when accessing program memory, three more dsp cycles are added to the program read due to the multiplexed nature of the external program/data bus. table 2-15 dsp program address space address size number of wait states description 0000 h -dfff h 56 kw 0 for read 1) 3 for write external program e000 h -efff h 4 kw 0 for read 1) 3 for write internal program ram (devided to four) - option for future implementation f000 h -fdff h 3.5 kw - not used fe00 h -feff h 0.25 kw 0 syne table rom ff00 h -ffff h 0.25 kw 0 internal boot rom peb 20560 functional block description semiconductor group 2-63 1997-11-01 2.7.3 control of external memories / registers the external data and program memories are accessed through a multiplexed data and program bus. this bus includes a 16-bit address bus (ca) and 16-bit data bus (cd). the dcu is generating the read and write controls for these memories and controls the input and output pads. the external bus is usually used for fetching program instructions, therefore its defined with program priority. it means that every external bus sequence starts with a program fetch (always zero wait states). if there is need for data access, the external bus sequence is extended to a minimum of 4 cycles in the following way: ? cycle 1 - program fetch ? cycle 2 - idle1 cycle ? cycle 3 - data access (can be extended up to 8 cycles = 7 wait states) ? cycle 4 - idle2 cycle if instead of a program fetch there is a program write, the oak receives three wait states (see program write diagram). the program write is always performed by the oak using the movd instruction (it ensures that a program write will never be in parallel to a data access). the movd instruction is a four cycle instruction therefore, due to the extra wait 1) for accessing the external data memory 0 to 7 waitstates can be selected. this leads to three to ten more dsp cycles for external data read and write. 2) if the dsp tries to write to the circular buffer in the same time that the pediu uses it, the pediu has higher priority. in this case, up to four more dsp cycles will be added to the access. the user should dedicate 0.5 kword of program ram for the monitor (the routine used by the emulator). table 2-16 dsp data address space address size number of wait states number of dsp cycles description 0000 h -03ff h 1 kw 0 1 internal xram 0400 h -3fff h 15 kw -- unused 4000 h -bfff h 32 kw 0-7 4-11 1) external data memory c000 h -dfff h 8 kw 0 1 oak memory mapped registers e000 h -efff h 4 kw -- unused f000 h -f0ff h 256 w 0 2) 1 2) circular ram buffer f100 h -f3ff h 0.75 kw -- unused f400 h - f7ee h 1 kw-16 0-7 4-11 1) emulation mail box (on cdi) f7f0 h -f7ff h 16 w 1 2 ocem registers f800 h -fdff h 1.5 kw -- unused fe00 h -ffff h 0.5 kw 0 1 internal yram peb 20560 functional block description semiconductor group 2-64 1997-11-01 cycles, this instruction is actually performed in seven cycles in the doc. if a movd instruction reads the data from an external data ram, its length will be increased in 3-11 cycles more, according to the external bus sequence. figure 2-34 external data/program read access clk c-bus prog itd09687 data c-bus idle idle w.s. w.s. cdpw cdpr cmbr cmbw cbr data program data cdb cab [0...15] [0...15] data address program address peb 20560 functional block description semiconductor group 2-65 1997-11-01 figure 2-35 external data write access clk c-bus prog itd09688 data c-bus idle idle w.s. w.s. cdpw cdpr cmbr cmbw cbr data program data cdb cab [0...15] [0...15] data address program address prog peb 20560 functional block description semiconductor group 2-66 1997-11-01 figure 2-36 external program write access due to movd itt10074 written data write address clk cdpr cdpw cab[0...15] cdb[0...15] program read write read idle1 idle2 program program peb 20560 functional block description semiconductor group 2-67 1997-11-01 figure 2-37 external boot rom read clk c-bus prog itd09690 data c-bus idle idle w.s. w.s. cdpw cdpr cmbr cmbw cbr data program data cdb cab [0...15] [0...15] data address program address peb 20560 functional block description semiconductor group 2-68 1997-11-01 2.7.3.1 memory configuration register (memconfr) the memory configuration register, memconfr, is a memory mapped register, at address c002 h , which controls the memory interface. in the following are its bit assignments: note: bits 15 3 are unused and are read as 0. dws - sets the number of wait states on external data space (0-7). dws can be read or write by the dsp. after reset it is set to 0007 h . wait-states external data space the wait-state generator is capable of generating programmable number (0-7) of w.s. when accessing the external data. the w.s. number can be programmed by setting the dws field, in the memconfr register, to the number of the desired w.s. when dws = 0 no wait states will be implemented. after reset the dws is set to 7. external boot rom (can be on cdi) the access to the eprom, during stand-alone boot, is with the same number of wait-states as written in dws. bit 1514131211109876543210 memconfr 0000000000000 dws peb 20560 functional block description semiconductor group 2-69 1997-11-01 2.7.3.2 test configuration register (testconfr) the test configuration register is memory mapped register, at address c003 h note: bits 8 0 are unused and are read as 0. pwb used as rams power down bypass. this bit can be read/write by the sw. cleared after reset. oake memory enable of the oak. this bit is the value of the oak memory enable signal (pmemenp) in the previous cycle. it enables observabilty of this signal. this bit is read only. cire circular buffer enable. this bit is the previous cycle value of the circular buffer enable signal which is combination of the oak pmemenp and the pediu request because they both can use the ram. this bit is read only. p3e, p2e, p1e, p0e program ram enables reflect the value of the bsn input of the four program rams for enabling observability. if the bsn inputs of the program rams are stuck to zero, the ram will work properly and the only effect will be more current. bit 15 14 13 12 11 10 9 8 testconfr pwb oake cire p3e p2e p1e p0e 0 bit 76543210 testconfr 00000000 peb 20560 functional block description semiconductor group 2-70 1997-11-01 2.7.4 emulation support the cdi board communicates with the combo with two main interfaces: ? control pins (boot, dbg, abortn, rstn). ? c-bus interface (for program ram, mail box and boot eprom) the control strap pins are inserted to the dcu which is responsible to send the right signals to the ocem module and the oak emulation interface pins. the communication protocol between the debugger and the monitor program is not protected from the case where user program, by mistake writes to the monitor space. in such a case the monitor routine will be corrupted with no way to recover. a write to the emulation mail box is prevented except for the following cases: ? during monitor routine (a write which is done by the emulator). ? during boot routine execution (code download). 2.7.5 interrupt handling and test support the oak user interrupts (int0, int1, int2, nmi) are asserted by the dcu. usually, the sources for the interrupts are the functional blocks but for testing, there is a way of inserting the interrupts from doc input pins. therefore, the interrupt sources are as follows: (tif if the test flag - see the testconf register). table 2-17 interrupt map interrupt source (tif = 0) source (tif = 1) int0 pcm-dsp interface = fsc ad8 int1 ad9 int2 m p mail box cs nmi wr bi ocem abort wait dcu ad7 peb 20560 functional block description semiconductor group 2-71 1997-11-01 2.7.6 run time statistics counter and register (statc and statr) the dsp performs its activities in a cyclic manner, which start with frame sync clock (fsc). it must finish the execution of the current activities before the beginning of the next frame sync. the dsp run time statistics is used by the user to estimate the work load on the dsp. by using this hw, the user can find very accurately the maximum time spent by the dsp from the fsc until it finished its job. the dsp statistics include an eight bit counter statc which is counting up every 1 m s. figure 2-38 usually, the statc is reset when there is a frame sync (fsc) rising edge. when the dsp finishes its tasks it reads the statc value. the time between two consecutive frame syncs is always 125 m s, therefore, if the dsp is working properly, the counter value should always be less then 125 m s. if the dsp failed to read the counter value and a new fsc rising edge has arrived, the counter is not reset. therefore, the dsp would read a value greater then 125. it means that the dsp failed to finish its tasks within the time frame of 125 m s. the statr register is added for helping the user to perform the statistics. statr is a general purpose 8-bit read/write register (its 8 most significant bits are always read as 0). the user program should perform statistics in the following way: ? the statc is reset upon detection of fsc rising edge. ? the dsp finishes its activities and reads the value of statc and statr. ? the dsp compares statc to the previous maximum value saved in statr. ? if the new value is larger, it should be written to statr. the system programmer can get the counter value via m p-mail box and thus can change the dsp program (for example, more conferences may be implemented). its10076 statr statc dsp dsp maximum-value register counter (in frame n) 1 reset by fsc of the frame n+1, only if the dsp has read the counter already m s peb 20560 functional block description semiconductor group 2-72 1997-11-01 registers definition: statc memory mapped address c004 h . read only counter. statc70 satistics count. the 8 msbs are unused and read as 0. reset upon detection of fsc edge if statc was read by the dsp since the last fsc. unchanged upon chip reset statr memory mapped address c005 h . 8-bit read/write general purpose register. msc70 max statistics count. the 8 msbs are unused and read as 0. unchanged upon chip reset. bit 15 14 13 12 11 10 9 8 00000000 bit76543210 statc7 statc6 statc5 statc4 statc3 statc2 statc1 statc0 bit 15 14 13 12 11 10 9 8 00000000 bit76543210 msc7 msc6 msc5 msc4 msc3 msc2 msc1 msc0 peb 20560 functional block description semiconductor group 2-73 1997-11-01 2.7.7 program write protection register (passr) if the user writes by mistake to the program ram, the dsp program may collapse. a protection is provided by means of a password which the user must write to the password register (passr) before writing into the program ram. passr must be written with the value f236 h for enabling a program write. if the value in passr is different from f236 h , the cdpw (external program ram write) is not issued during a movd instruction. memory mapped address c006 h . 16-bit read/write register reset value - 0000 h note: the boot routine automatically sets the value of passr to f236 h for enabling the download of data to the program ram. after the download, the boot routine writes 0000 h to passr for enabling the program protection. this mechanism is bypassed during trap/bi handler in order to enable the monitor to change the program. 2.7.8 serial (via jtag) emulation configuration register (jconf) this register determines the emulation configuration. memory mapped address c007 h . 2-bit read/1 bit write register reset value - 8000 h (except bit 14 which is determined by strap) aborti this bit is read/write. when set to 1 the abort is as in parallel emulation (i.e. via abort pin). when resets to 0 the abort function is implemented via tdi pin (see seib chapter for more details). active this bit is read only, it gets the inverted value of bit 12 of c-bus (cdb12/seibdis) at the rising edge of dreset , when it used as a strap. when 1 it means that seib is active (i.e. emulation is serial via jtag). when 0 seib is not active, i.e.emulation is parallel. bit 15 0 passr bit 15 14 13 0 jconf aborti active peb 20560 functional block description semiconductor group 2-74 1997-11-01 2.7.9 boot support the boot is a process which loads the external program ram with the dsp program. there are three methods of booting the system: ? emulation boot a boot sequence which loads the monitor (bi routine) to the program ram. this routine enables the pc emulator to control the dsp. ? rom boot downloading code directly from an external boot rom to the program ram. ? m p boot a boot sequence which loads the program ram from the m p through the m p mail box. the boot is controlled by a boot routine which resides in the internal dsp program rom. this routine is starting to be executed upon chip reset according to the condition of the strap pins: note: when the strap pins, cdb0/boot, cdb1/dbg and cdb2/rom, are not driven externally during reset, they are driven internally by an internal pull-downs. if a fixed external pull-up is applied on a strap, a pull-up resistor of 5 k w is required. 2.7.9.1 boot sequence the boot always starts immediately after reset with an execution of the instruction brr-3 by the oak. due to the fact that during reset the oak pc register points to address 0000 h , the brr-3 instruction performs a jump to address fffe h . this address is on the top of the program rom. at this address there is a branch instruction to the beginning of the boot routine (br ff00 h ). at the beginning of the boot, the status of the strap pins is checked by reading the contents of the bootconf and jconf register. table 2-18 boot mode boot strap dbg strap rom strap no boot 0 dont care dont care usual reset which starts fetching from the address 0000 h of the external program ram. boot 1 1 0 emulation boot boot 1 0 1 rom boot boot 1 0 0 m p boot not defined 1 1 1 forbidden peb 20560 functional block description semiconductor group 2-75 1997-11-01 according to the strap pins, the download of the program ram starts, and also the type of emulation (in case of emulation boot i.e. parallel/serial). 2.7.9.2 emulation boot the emulation boot supports the down-loading of software code from an external dual ported ram (mail box buffer), loaded earlier by the debugger host, to the program ram. two specified addresses in the mail box have to be with following data 2.7.9.3 boot procedure the debugger should activate the boot and dbg strap pins, on reset negation. as a result, the program jumps to the boot routine. the mail box is accessed (read) using the data memory control signal. the software uses the movd command of the oak to write to the program ram. the last instruction of the boot routine is trap to pass control to the monitor program. 2.7.9.4 boot rom the purpose of this mode is to down-load the application program from a slow memory device to the program ram in order to execute the program after boot from the ram with zero w.s. the external hardware will include eprom or rom which will be connected to the cbr signal and a program ram which will be connected to the cdpw . the specified address in the eprom will include: ? control word ? the number of words to be loaded. ? the first program ram address to load to. if the boot and rom strap pins are active during reset negation and the dbg is not active, the boot routine starts performing the boot rom download. the epm bit in the bootconf register, is set by the hw. as a result, all read transactions, in movp instructions, will be from the boot eprom which means that the boot eprom will be located in the program address space. the movp instruction will put the data in a temporary location in the data memory, from which it will be transferred to the external ram using movd instruction. the rom data structure is illustrated bellow, this structure will enable the user to down-load a few blocks of code from the eprom into different locations in the table 2-19 address contents value 0xf400 the number of words to be loaded. 0xf401 the first program ram address to load to. peb 20560 functional block description semiconductor group 2-76 1997-11-01 destination ram. the control word will tell the down-loading program weather to finish loading (ffff h ) or to continue with the next block (0000 h ) except for the first block were the control word will contain program ram address to jump to at the end of the down-loading. at the end of the down - load procedure the epm bit must be cleared by the boot routine, by writing to it. as a result, resuming to the normal memory mapping and the regular control signal will be generated to the external data memory. the next instruction will be a branch to the address, specified in the eprom first address. 2.7.9.5 m p boot the m p boot procedure is as follows: ? oak boot routine: write to ocmd (mail box command register) the command start loading program ram ? m p: as a result, the m p writes the m p mail box command start boot procedure. ? oak boot routine: clears the mbusy bit ? m p: performs the command write program memory command. ? oak boot routine: performs the write to the program ram and verifies that the data was written correctly. then the mbusy is cleared. ? m p: performs the next write command. this process continues until all the code is loaded. then, instead of a write command, the m p issues the command: finish boot procedure. as a result, the oak boot routine clears the mbusy bit and branches to address 0000 h . table 2-20 eprom/rom data structure start address number of words ram address data to be loaded control word number of words ram address data to be loaded control word number of words ram address data to be loaded control word peb 20560 functional block description semiconductor group 2-77 1997-11-01 if something went wrong during the download, the oak sends the command error during boot and then waits for the command start boot procedure from the m p. when receiving this command, the oak boot routine restarts the boot procedure and waits for the write program memory command. 2.7.9.6 mail box instructions format for enabling the m p boot, there are some predefined opcodes used by the boot routine. these opcodes are valid only for the boot routine. when the user program is executed later, these opcodes have no affect. there are two separate sets of opcodes, one for the m p mail box and the other for the oak mail box. m p opcodes finish boot procedure description: finish the boot procedure (the m p has finished loading the program ram). 2.7.9.7 write program memory command description: write the content of registers mdt1- mdt num (num=15) to the program ram address (mdt0) - (mdt0 + num - 1), consecutively. operation: write to program memory from address within mdt0 up to (mdt0 + num - 1). the data to be written is taken from mdt1 to mdt5. the content of mdt1 is written to the address which resides within mdt0, the content of mdt2 is written to the address (mdt0 + 1), and so on. notice that allowed values of num are 15. example: mdt0 = 20a0 h opcode 00101011 (num = 3). it will result with: program ram address 20a0 h mdt1 program ram address 20a1 h mdt2 program ram address 20a2 h mdt3 note: the program ram is write protected. it can be written only if the write is enabled by writing a special code to a register within the dcu (see the dcu description for more details). 000001 1 1 00101 num peb 20560 functional block description semiconductor group 2-78 1997-11-01 start boot procedure description: start the boot procedure. used for starting the boot procedure (as response to the oak command start loading program ram) and for restarting the boot if something failed during the boot (as response to the oak command error during boot). 2.7.9.8 oak opcodes the oak opcodes enable the oak to send commands to the m p. start loading program ram description: this command requests the m p to start loading the program ram. it is used by the boot routine to initiate the load of the program ram. note: the int2 vector is used by the boot routine in a pending method (reading the st2), therefore, the int2 interrupt vector can be written without influencing the boot procedure. error during boot procedure description: this command requests the m p to stop the download due to an error (which may be fixed by starting the download from the beginning). the err field is the error status as follows: 000 a m p command different then nop, finish boot or write program arrived. 001 the data written to the program was not read back (result of a test of the first few loaded words to the program ram). 01010101 00000111 01110err peb 20560 functional block description semiconductor group 2-79 1997-11-01 2.7.9.9 boot configuration register (bootconf) the boot configuration register, bootconf, is a memory mapped register at address c001 h * written as dont care, read as 0 epm this bit indicates that the chip is in eprom boot mode. it is set when boot strap pins are active, the dbg strap pin is inactive and the rom strap is active on reset negation. this bit can be read/write by the user. while epm bit is set, every read during movp instruction is done from the boot rom instead of the program space. 2.7.9.10 the bootroutine following is the bootroutine which resides in the internal bootrom. .format 10000,1000 .equ iopage 0xc0 ; memory mapped i/o page .equ bootconf 0x01 ; bootconf register offset address .equ memconf 0x02 ; memconf register offset address .equ testconf 0x03 ; testconf register offset address .equ status1 0xf7fe ; ocem status1 register .equ emumb 0xf400 ; emulation mail box address .equ ocemtracebuff 0x0010 ; ocem trace buffer length .equ ocemadd 0x45 ; <<<< temporary number .equ version 0xd0c0 ; chip version .equ monitor 0x7c00 ; monitor address (31k-32k) .equ bootconfadd (iopage<<8) | bootconf .equ br_code 0x4180 ; branch opcode .equ ocmd 0x50 ; oak mail box command register .equ obusy 0x51 ; oak mail box busy bit .equ odt0 0x52 ; oak mail box data reg 0 .equ mcmd 0x40 ; micro-processor mail box command register bit 15 14 13 12 11 10 9 8 bootconf epm******* bit 76543210 bootconf ******** peb 20560 functional block description semiconductor group 2-80 1997-11-01 .equ mbusy 0x41 ; micro-processor mail box busy bit .equ mdt0 0x42 ; micro-processor mail box data reg 0 .equ mdt0_add 0xc042 ; micro-processor mail box data reg 0 .equ mdt1_add 0xc044 ; micro-processor mail box data reg 1 .equ mb_nop 0x0 ; mail-box nop .equ finish_boot 0x7 ; mail-box finish boot command .equ start_boot 0x55 ; mail-box start boot procedure command .equ write_prog 0x28 ; mail-box write program .equ start_load 0x7 ; mail-box start prog. load command .equ mcmd_error 0x70 ; error in micro-processor command .equ prog_error 0x71 ; program data verification failed .equ passr_reg 0xc006 ; passr register address .code s_main .use s_main .org 0xff00 bootrtn: ;########################################################## ; initialization ; the mail box on the cdi is a slow memory, therefore, wait ; states are needed. if the doc will run in a frequency higher ; then 40 mhz 7 ws will be needed. therefore, the default of ; 7 ws in dws field of memconf is not changed. lpg #iopage mov #0x0,r5 ; r5=0 mov ##0x200,sp ; put a default value in sp mov ##passr_reg,r1 ; passr register address set ##0xf236,(r1) ; disable program protection ;########################################################## ; this check decides what kind if boot is it. ; if it's a rom boot. epm bit is active. epm is the msb ; of the bootconf, therefore, after reading it to the ; accumulator, the sign extension will create a negative ; value if epm is set (m flag will be activated) mov bootconf,a0 ; read the epm bit. br rom_boot,lt peb 20560 functional block description semiconductor group 2-81 1997-11-01 ; if the dbg flag in the ocem is active, it is an emulation ; boot. the dbg flag is in status1 register, bit 15 (msb). ; therefore, if it is set, a transfer to the accumulator will ; make the accumulator negative. mov ##status1,r0 ; status1 address to r0 mov (r0),a0 ; read the dbg bit. br emu_boot,lt ;########################################################## ; micro-processor boot ; ; after the read of the micro-processor mail-box, the mbusy bit ; is set and then the micro-processor is loading the next data. ; in parallel to this load, the boot routine verifies that the ; data loaded to the program ram is correct. load #0x2,stepi ; stepi = 2 mov ##start_load,r0 ; code of start load command mov r0,ocmd ; command to ocmd register ; the micro-processor should respond with start boot procedure ; command. ; the start boot procedure command is added always but it is ; realy needed in a special case. it is when the download ; verification fails. in this case, the boot has to restart ; but meanwile, the micro-processor has started writing the ; next data and may write the write command. therefore, in ; this case the oak waits until the micro-processor receives ; the error command and reacts with the start boot procedure ; command. int2_poll1: rep #0x6 ; wait until int2 is reset after nop ; a clear of busy bit tst1 ##0x2000,st2 ; check if int2 is set brr int2_poll1,neq ; wait for int2 mov mcmd,a0 ; read micro-processor command mov r5,mbusy ; clear busy bit peb 20560 functional block description semiconductor group 2-82 1997-11-01 cmp ##start_boot,a0 ; check if it's "start boot" brr int2_poll1,neq brr int2_poll2 clear_busy: mov r5,mbusy ; clear busy bit rep #0x6 nop ; delay for making sure that ; the int2 signal was reset ; due to the clear of mbusy int2_poll2: tst1 ##0x2000,st2 ; check if int2 is set brr int2_poll2,neq ; wait for int2 mov mcmd,a0 ; read micro-processor command mov mcmd,a1 ; copy also to a1 and #0xf8,a0 ; clear 3 lsb of a0 cmp ##0x28,a0 ; check if it's write mem. command brr write_mem,eq cmp #0x7,a1 ; check if it's finish boot br finish_eboot,eq ; goto emulation boot finish mov ##mcmd_error,r0 ; error has occured if reached here mov r0,ocmd brr clear_busy ; a1 include the micro-processor command contents. the 3 lsb are ; the number of data registers to be loaded. the first data ; register (mdt0) contains the address of the first write data. write_mem: mov #0x0,r3 ; first address of xram and #0x7,a1 ; leave only the number of words to load dec a1 ; prepare a1 for the rep (number of loops ; is a1 + 1) mov ##mdt0_add,r1 ; mdt0 address to r1 mov (r1)+s,r4 ; mov start load address from mdt0 ; to r4 and advance r1 to mdt1 peb 20560 functional block description semiconductor group 2-83 1997-11-01 mov r4,a0 ; save load address in a0 bkrep a1l,>%end_copy-1 mov (r1)+s,y ; copy mail box registers to xram mov y, (r3)+ %end_copy: mov ##mdt1_add,r1 ; mdt0 address-value to r1 rep a1l movd (r1)+s,(r4)+ ; download to program ram mov r5,mbusy ; clear busy bit for enabling the ; the micro processor to load ; the next data ; the time until the micro-processor loads the next data is used ; for verifying that the data was loaded correctly mov a1l,r2 ; number of load words-1 to r2 modr (r2)+ ; number of load words in r2 mov #0x0,r3 ; first address of xram check_ram: movp (a0l),a1 ; read loaded program ram cmp (r3)+,a1 ; compare to saved mail box in xram brr check_err,neq ; data in prog. ram not equal to mb reg. inc a0 ; point to next prog. ram address modr (r2)- brr check_ram,nr brr int2_poll2 ; an error has occured during program ram verification check_err: mov ##prog_error,r0 ; program data error has occured mov r0,ocmd brr int2_poll1 ; wait for resume of boot procedure ; by the micro processor start boot ; procedure command ; finish the micro-processor boot peb 20560 functional block description semiconductor group 2-84 1997-11-01 finish_eboot: ; enable program write protection ;********************************************* mov ##passr_reg,r1 ; passr register address mov #0x0,r2 ; r2 = 0 mov r2,(r1) ; enable program write protection mov r5,mbusy ; clear busy bit br 0x0 ;########################################################## ; rom boot ; ; during rom boot the movp command is reading from the boot ; rom. rom_boot: ; read the rom parameters: ;************************** mov #0x0, a1l ; rom first address movp (a1l), lc ; start address to jump to at the end. mov #0x0,r3 ; first address of xram rom_load: inc a1 movp (a1l), r2 ; number of words to load. inc a1 movp (a1l), r4 ; ram address to load to. inc a1 ; load user program from rom to the program ram: ;************************************************ mov a1l, r5 ; load the pointer rom_block: movp (r5)+, (r3) ; down load one word movd (r3),(r4)+ modr (r2)- ; decrement number of words peb 20560 functional block description semiconductor group 2-85 1997-11-01 brr rom_block,nr mov r5, a1l movp (a1l), a0l ; load the control word brr rom_load, eq ; if equal to zero load the next block rst ##0x8000,bootconf; reset the epm bit in bootconf register ; enable program write protection ;********************************************* mov ##passr_reg,r1 ; passr register address mov #0x0,r2 ; r2 = 0 mov r2,(r1) ; enable program write protection mov lc, pc ; branch to the address specified in the ; eprom parameters nop ; nop 1 - has to be added after mov to pc nop ; nop 2 - has to be added after mov to pc ;########################################################## ; emulation mode ; ; the emulation boot loads the monitor routine for the emulator. ; the start addresses of the mail box are as follows: ; f400 - number of words to load ; f401 - the first program ram address to load to. emu_boot: mov ##emumb, r0 ; emulation mail box address mov (r0)+, r3 ; number of words to load. mov (r0)+, r5 ; ram address to load to. ; load nop to the reset vector ;***************************** mov #0x0, r1 mov #0x0, r4 ; 0 is nop opcode mov r4,(r1) ; put 0 in xram address 0 movd (r1),(r4)+ movd (r1),(r4)+ peb 20560 functional block description semiconductor group 2-86 1997-11-01 ; load the branch instruction opcode to bi/trap vector ;******************************************************* mov ##br_code, r2 mov r2, (r1) movd (r1), (r4)+ mov r5,(r1) movd (r1),(r4)+ ; load the monitor program from mailbox to the program ram: ;********************************************************* modr (r3)- ; loop count rep r3 movd (r0)+, (r5)+ ; push on the stack the following information: ;********************************************* push ##ocemadd push ##ocemtracebuff push ##bootconfadd push ##version ; enable program write protection ;********************************************* mov ##passr_reg,r1 ; passr register address mov #0x0,r2 ; r2 = 0 mov r2,(r1) ; enable program write protection trap ;.org 0xfff8 nop ; should be fff8 nop ; should be fff9 nop ; should be fffa nop ; should be fffb nop ; should be fffc nop ; should be fffd br bootrtn peb 20560 functional block description semiconductor group 2-87 1997-11-01 2.7.10 sine table rom the sine table rom is a 256 16 bit word rom, which resides in the dsp program space, between the addresses: fe00 h - feff h . it contains 256 samples of one sine cycle. these samples were taken every fixed step of 2 p /256, and their value is represented in fixed-point. note: for details please refer to the application note how to use the doc sine table. peb 20560 functional block description semiconductor group 2-88 1997-11-01 2.8 pcm-dsp interface unit (pediu) 2.8.1 general description the pediu gives the dsp access possibility to 64 down-stream pcm b-channels, that come from the two elics, and the possibility to drive upstream 64 pcm b-channels that go back to the elics. in general, the pediu feeds a bidirectional circular buffer with b-channels. they are written into the buffer by the pediu and read by the dsp in downstream direction, and written into the buffer by the dsp and read out by the pediu in the upstream direction. a possible flow of b-channels between elic1 and pediu port1 is demonstrated as an example in figure 2-39 : ? the b-channel b1 coming from iom-2 interface on du00 is switched by elic1 via internal loop to cfi port1 dd11 line. each loop requires one time-slot on the pcm highway (b*). ? the b-channel b2 coming from pcm highway on the rxd0 line is switched by elic1 to cfi port1 dd11 line. ? the pediu reads the b-channels, b1 and b2, in. ? the pediu writes the b-channels b3 and b4 out on the du11 line. ? elic1 switches b3 to the iom-2 interface on dd00 via its internal loop. ? elic1 switches b4 via txd0 to the pcm highway. note: every above elic loop utilizes one time-slots on the pcm highway (i.e. b1* and b3*). if the elic is programmed to be in high impedance state during those time-slots, they (b1* and b3*) can be used for other purpose (e.g. for signaling by a sacco). the pediu is connected with both elics: with port0 of elic0 and with port1 of elic1. peb 20560 functional block description semiconductor group 2-89 1997-11-01 figure 2-39 example: flow of b-channels between elic1 and pediu two data streams with 32 successive time-slots each, or one data stream of 64 time-slots, come every 125 m s from epic0 and epic1 in data downstream direction. they are converted into 8-bit parallel values, or into 16-bit a-/ m -law linear values, and stored via a dma controller in a ram (the circular buffer). the ram contains 128 words for received data (dsp-in) configured in 4 in blocks, and 128 words for data to be transmitted back to the upstream (data-out), configured in 4 out blocks. while the dma controller writes the data of the current downstream frame (frame n) into one half of dsp-in block, the dsp accesses the second half of dsp-in, which contains b-channels values of the previous frame (frame n-1). at the same time the dma reads data from one half of the dsp-out block into the upstream, while the dsp writes into the other half of dsp-out; the data to be read into the upstream in the next frame (frame n + 1). all accesses to the circular buffer are synchronized by fsc (frame synchronization clock) and by dcl (data clock). for more information on the process, which takes place every frame, see figure 2-40 . its10092 b3 b1 dd10 du10 port 0 r iom -2 elic r -1 port 0 rxd0 txd0 cfi pcm port 1 du11 dd11 pcm b3* b1* b2 b3* b1* b4 b1 b2 pediu b3 b4 in1 out1 dsp peb 20560 functional block description semiconductor group 2-90 1997-11-01 figure 2-40 accesses to the pediu ram (circular buffer) at two consecutive frames itd10093 dsp - in0 - 0 dsp - in0 - 1 dsp - in1 - 0 dsp - in1 - 1 dsp - out0 - 0 dsp - out0 - 1 dsp - out1 - 0 dsp - out1 - 1 frame n from dma frame n to dma to dsp frame n - 1 from dsp frame n + 1 256 x 16-bit ram as 8 x 32-word blocks = 4 x in + 4 x out ram frame n dsp - out1 - 0 dsp - out1 - 1 dsp - out0 - 1 dsp - in1 - 0 dsp - in1 - 1 dsp - in0 - 1 dsp - out0 - 0 dsp - in0 - 0 ram frame n + 1 itd10094 to dsp frame n frame n + 2 from dsp frame n + 1 from dma frame n + 1 to dma peb 20560 functional block description semiconductor group 2-91 1997-11-01 the index of each frame (n, n + 1, etc.) indicates when the frame would be written to the up stream or read from the down stream. the process described in the picture recurrents every 2 frames. the pediu contains: ? a serial-parallel and an a-/ m- law to linear converters for receive (in) direction ? a linear to a-/ m- law and a parallel-serial converter for transmit (out) direction ? a multichannel dma controller for accessing the ram ? a bypass and tri-state logic ? rom, ram and dsp interface the bypass logic of the dsp-in stream selects which b-channels will be converted into linear values, and which b-channels will bypass the a-/ m- law to linear converter. every consecutive 4 b-channels are controlled by one bypass flag in a special register. one 16-bit register controls 64 dsp-in b-channels. the out streams values (8-bit coded or 16-bit linear) are controlled similarly in dsp-out direction. another similar 16-bit register is dedicated for controlling the tri-state buffers of the two out streams (out1 and out2). this register defines which out-stream b-channels are valid, and which are not. here the resolution is also of 4 b-channels per bit. these three registers can be accessed by the dsp, for read and write. the pediu-rom is of 512 words. it contains the linear values of all the possible a-law and m -law values. it is used to convert words from a-/ m -law to linear in the dsp-in direction. the opposite conversion, from linear to a-/ m -law in the dsp-out direction, is done by a special logic circuit. peb 20560 functional block description semiconductor group 2-92 1997-11-01 figure 2-41 block diagram of the pcm-dsp interface unit (pediu) note: a) after reset, both converters (a-/ m -law to linear and linear to a-/ m -law) are enabled, and all the dsp-out time-slots are in tri-state. b) the pediu access priority to the circular buffer, is higher then access priority of the dsp. if the dsp tries to access the circular buffer concurrently, with the pediu, it will be delayed by a wait signal from the dcu (dsp bus control unit), till the end of the pedius access. itb10095 converter parallel serial/ parallel/ serial converter to linear -law a-/ m 8 16 8 16 8 bypass flags linear -law m a-/ to 16 8 8 dma controller control logic and tristate flags 256 x 16 bit a-law 256 x 16 bit m -law rom in0 in1 fsc dcl out0 out1 tsc r iom -multiplexer dsp- dsp- frame n pediu-ram dsp-in0-0 dsp-in1-0 dsp-in0-1 dsp-in1-1 dsp-out0-0 dsp-out1-0 dsp-out0-1 dsp-out1-1 control logic bus a & d frame n-1 frame n+1 dsp oak fsc circular buffer 256 x 16-bit ram in 4 x 64-word blocks dcu pediu syncronized fsc pediu register write pediu register read uwritep ureadp logical data flow 16 d-bus a & control bus mail-box m p ram_write ram_read bypass flags peb 20560 functional block description semiconductor group 2-93 1997-11-01 2.8.2 pediu internal registers the following section describes the pediu internal registers. the following details are specified for each register: name, function of each bit, registers schema, read and write addresses and method of write into the register or of read the content. 2.8.2.1 pediu control register (ucr) this register determines the work mode of the pediu. it also determines whether the pediu is in a working or idle mode. the ucr has 5 bits. after reset all bits are 0. address: 0xc100 m20 pediu work mode the definition of each bit can be seen in table 2-21 amul a-law or m -law activep active (idle not). note: bits 15 5 are unused and are read as 0. a detailed description of the ucr follows on the next pages: 15 14 13 12 11 10 9 8 00000000 76543210 0 0 0 activep amul m2 m1 m0 peb 20560 functional block description semiconductor group 2-94 1997-11-01 table 2-21 work modes specifications of the pediu mode bits mode data rate [mbit/s] dcl [mhz] no. of input- streams time- slots per frame (in each input stream) number of in and out blocks in circular buffer (pediu ram) notes m2 m1 m0 0 0 0 0 2 4 double clock 2 32 4 in blocks 4 out blocks iom-2 compatible 0011 2 2 single clock 2 32 4 in blocks 4 out blocks 0102 4 4 single clock 2 first 32 from 64 time-slots 4 in blocks 4 out blocks pediu can handle only first 32 time-slots of each input stream frame. 0113 4 4 single clock 1 64 2 in blocks 2 out blocks pediu can handle all 64 time-slots of the frame, but only of in-stream 0. 1004 8 8 single clock 1 first 64 from 128 time-slots 2 in blocks 2 out blocks pediu can only handle the first 64 time-slots of the frame, and only of in-stream 0. 1 0 1 5 pediu test mode. used to test pediu rom and pediu ram. pediu in and out streams are in idle mode. peb 20560 functional block description semiconductor group 2-95 1997-11-01 note: C the data rate of each output stream is identical to the one of an input stream, and the number of output streams is identical to the number of input streams in any mode. C in mode0 dcl is a double clock, which means that a new bit streams in every 2 dcl cycles. in modes 1, 2 and 3 dcl is a single clock. C in all modes fsc = 8 khz. C in modes 0, 1, 2, 3 dsp clock rate can be 20 mhz, 30 mhz or 40 mhz. in mode 4 dsp clock rate should be 40 mhz C dcl rate may be 2.048 mhz, 4.096 mhz or 8.192 mhz. C in modes 2 and 3 there are 64 time-slots in each frame. in mode 2 the circular buffer is divided into 4 in blocks and 4 out blocks of 32 words each (in the same way as in mode0), so only the first 32 time-slots, coming in each in-stream, can be handled by the pediu. unlike mode 2, in mode 3 the circular buffer divided into 2 in blocks and 2 out blocks of 64 words each, so handling of all 64 time-slots of the frame is possible, but only of the in0 input-stream. the division of the circular buffer in mode 4, is as in mode 3. the exact address space of each circular buffer block, as a function of the pediu work mode, can be seen in table 2-22 . table 2-22 address spaces of circular buffer blocks as a function of the pediu work mode mode in blocks out blocks in0 - 0 in0 - 1 in1 - 0 in1 - 1 out0 - 0 out0 - 1 out1 - 0 out1 - 1 modes 0, 1 & 2 0x00 - 0x1f 0x20 - 0x3f 0x40 - 0x5f 0x60 - 0x7f 0x80 -0x9f 0xa0 - 0xbf 0xc0 - 0xdf 0xe0 - 0xff mode 3 & 4 0x00 - 0x3f - 0x40 - 0x7f - 0x80 - 0xbf - 0xc0 - 0xff - peb 20560 functional block description semiconductor group 2-96 1997-11-01 figure 2-42 block structure of circular buffer (pediu ram) in different pediu work modes amul - bit 3 in ucr amul bit defines whether pediu applies a-low to linear conversion on the input stream and linear to a-low conversion on the output stream, or m -low to linear conversion on the input stream and linear to m -low conversion on the output stream. amul = 0: a-low conversion. amul = 1: m -low conversion. note: a/ m -low to linear conversion and linear to a/ m -low conversion can be bypassed by programming registers ubpir and ubpor. for details see section 2.8.2.3 . activep - bit 4 in ucr activep bit defines whether or not the pediu is in idle mode. when in idle mode the pediu is paralyzed, and no activities may take place inside it - including dma accesses to the pediu ram. activep = 0: pediu is in idle mode. activep = 1: pediu is active. note: when the pediu is in idle mode (activep = 0), access of the dsp to the pediu ram is enabled. itd10096 dsp - in0 - 0 dsp - out0 - 0 dsp - out1 - 0 00 3f 40 7f 80 c0 bf ff h dsp - in0 - 1 dsp - in1 - 0 dsp - out0 - 1 dsp - out1 - 1 dsp - in1 - 1 9f a0 5f 60 20 1f df e0 pediu-ram pediu work modes 0, 1 and 2 pediu work modes 3 and 4 ff bf c0 7f 80 40 3f dsp - out0 - 0 dsp - out0 - 1 dsp - in0 - 1 00 pediu-ram dsp - in0 - 0 h h h h h h h h h h h h h h h h h h h h h h h peb 20560 functional block description semiconductor group 2-97 1997-11-01 2.8.2.2 pediu status register (usr) the usr is the status register of the pediu. its content may be used by the programmer to find out the status of the pediu. this register has only one bit - the most significant bit: cb. dsp reads usr from the address 0xc101. the 15 lsbs will be read as 0. it is not possible to write to usr. after reset the usr register is 0000 h . cb current block the cb bit indicates the state of the circular buffer during the current frame. cb indicates the blocks of the circular buffer the accessed by the pediu in this frame and those that should be accessed by the dsp. the exact meaning of cb depends on the work mode of the pediu, as this mode defines the circular buffer structure, as can be seen in table 2-22 . cb = 0: when pediu mode is 0, 1 or 2: during the current frame the pediu reads from circular buffer blocks dsp-out0 - 0 and dsp-out1 - 0 and writes into dsp-in0 - 0 and dsp-in1 - 0. when pediu mode is 3 or 4: during the current frame the pediu reads from circular buffer blocks dsp-out0 - 0 and writes into dsp-in0 - 0. for more details see table 2-22 , which explains the circular buffer block. cb = 1: when pediu mode is 0, 1 or 2: during the current frame the pediu reads from circular buffer blocks dsp-out0 - 1 and dsp-out1 - 1 and writes into dsp-in0 - 1 and dsp-in1 - 1. when pediu mode is 3 or 4: during the current frame the pediu reads from circular buffer blocks dsp-out0 - 1 and writes into dsp-in0 - 1. for more details see table 2-22 , which explains the circular buffer block structure in each mode. cb is inverted at the start of every new frame, immediately after rising edge sampling of fsc by the pediu. after reset or when the pediu is in idle mode (ucr:activep = 0), cb is updated to 0. in the first frame after pedius activation (set ucr:activep to 1), cb will be 1. figure 2-43 describes the function of cb when pediu work mode is 0, 1 or 2 and figure 2-44 describes the function of cb when pediu work mode is 3 or 4. bit 15 0 usr cb000000000000000 peb 20560 functional block description semiconductor group 2-98 1997-11-01 note: it is unnecessary for the user to read the cb bit during regular work with the pediu, in purpose to access the right block in the circular buffer. during regular work, (in modes 0, 1, 2, 3 or 4, when the pediu is active), the pediu uses the cb signal internally for both dma accesses to the circular buffer and dsp accesses to the circular buffer. in the case of dsp access to the circular buffer, the pediu disregards one of the address bits supplied by the dsp, and use cb instead. in this way any dsp access to the circular buffer accesses a permissible block, automatically. for more details refer to section 2.8.5.3 . actually, the pediu status register is used only for pediu testing. peb 20560 functional block description semiconductor group 2-99 1997-11-01 figure 2-43 connection between cb bit and accesses to the circular buffer blocks in pediu work mode 0, 1 or 2 itd10097 dsp - in0 - 0 dsp - in0 - 1 dsp - in1 - 0 dsp - in1 - 1 dsp - out0 - 0 dsp - out0 - 1 dsp - out1 - 0 dsp - out1 - 1 read by dsp written by dsp cb = 0 00 1f 20 in0 stream. written by pediu in1 stream. written by pediu 5f 60 3f 40 out0 stream. pediu read by 7f 80 9f a0 read by out1 stream. pediu e0 c0 df bf ff out1 stream. pediu read by read by out0 stream. pediu in1 stream. pediu written by in0 stream. written by pediu a0 df ff e0 bf c0 80 9f 7f 60 5f 40 3f dsp - out0 - 1 dsp - out1 - 0 dsp - out1 - 1 dsp - in1 - 0 dsp - in1 - 1 dsp - out0 - 0 00 1f 20 dsp - in0 - 1 dsp - in0 - 0 read by dsp written by dsp cb = 1 h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h h peb 20560 functional block description semiconductor group 2-100 1997-11-01 figure 2-44 the connection between cb bit and accesses to the circular buffer blocks in pediu work mode 3 or 4 itd10098 dsp - in0 - 0 dsp - in0 - 1 dsp - out0 - 0 dsp - out0 - 1 read by dsp cb = 0 00 in0 stream. written by pediu 3f 40 out0 stream. pediu read by 7f 80 c0 bf ff h ff read by pediu c0 bf out0 stream. 7f 80 40 3f dsp - out0 - 1 dsp - out0 - 0 dsp - in0 - 1 pediu in0 stream. written by 00 dsp - in0 - 0 written by dsp read by dsp cb = 1 written by dsp h h h h h h h h h h h h h h h peb 20560 functional block description semiconductor group 2-101 1997-11-01 2.8.2.3 pediu input stream bypass enable register (uisbper) this register defines: ? which time-slots, coming in the input streams, will be converted to linear values by the a-/ m -law to linear converter ? which time-slots will bypass this converter. the uisbper is a 16-bit register, where each bit controls 4 sequential time-slots and determines which time-slots will be converted or not. after setting any of uisbper bits to 1, its related 4 sequential time-slots will bypass the a-/ m -law to linear converter. after resetting any of uisbper bits (to 0), its related 4 sequential time-slots will be converted by the a-/ m -law to linear converter. for each bit in uisbper 0 convert the related sequential time-slot quadruplet from a-/ m -law to linear word. 1 let the related sequential time-slot quadruple to bypass the a-/ m -law to linear converter. the pediu work mode determines the quadruplet (4 sequential time-slots) that each uisbper bit is in charge of. when the pediu works in mode 0 or 1 and 2 the uisbper is divided into two parts. the 8 lsbs controls the 32 time-slots per frame (when working in mode 2 these are the first 32 time-slots from 64), coming in in0 input stream. the 8 msbs controls the 32 time-slots per frame, coming in in1 input stream. when working in mode 3 or 4 uisbper is not divided, and all its 16 bits controls the 64 time-slots, coming in in0 input stream. in mode 4 these are the first 64 timeslots from 128. table 2-23 describes which time-slot quadruplet is controlled by each uisbper bit in each pediu work mode. 15 14 13 12 11 10 9 8 uisbpe15 uisbpe14 uisbpe13 uisbpe12 uisbpe11 uisbpe10 uisbpe9 uisbpe8 76543210 uisbpe7 uisbpe6 uisbpe5 uisbpe4 uisbpe3 uisbpe2 uisbpe1 uisbpe0 table 2-23 specification of the time-slot quadruplet controlled by each bit in uisbper, in the different work modes of the pediu uisbper bit mode 0/1/2 mode 3/4 input stream time-slots input stream time-slots isbpe0 in0 0-3 in0 0-3 isbpe1 in0 4-7 in0 4-7 isbpe2 in0 8-11 in0 8-11 isbpe3 in0 12-15 in0 12-15 peb 20560 functional block description semiconductor group 2-102 1997-11-01 after reset all bits of uisbper are 0. setting resetting and reading uisbper uisbper has a special method of setting and resetting its bits. both uisbper reset instructions and uisbper set instructions are implemented by the dsp write instruction of a word that indicates the bits that should be set when it is a uisbper set instruction, and which bits should be reset when it is a uisbper reset instruction. the only difference between the set instruction and the reset instruction is the address that this word is being written to: ? for a set instruction the address of the dsp write instruction should be 0xc102 ? for a reset instruction the address of the dsp write instruction should be 0xc103. written word values are such that: ? every 1 in the written word indicates that the compatible bit in uisbper should be set or reset, depending on the address ? every 0 in the written word indicates that the compatible bit in uisbper should not be changed. note: the term compatible bit means that bit0 (lsb) of the written word determines if bit isbpe0 of uisbper will be set/reset or unchanged; bit1 determines isbpe1 and so on. isbpe4 in0 16-19 in0 16-19 isbpe5 in0 20-23 in0 20-23 isbpe6 in0 24-27 in0 24-27 isbpe7 in0 28-31 in0 28-31 isbpe8 in1 0-3 in0 32-35 isbpe9 in1 4-7 in0 36-39 isbpe10 in1 8-11 in0 40-43 isbpe11 in1 12-15 in0 44-47 isbpe12 in1 16-19 in0 48-51 isbpe13 in1 20-23 in0 52-55 isbpe14 in1 24-27 in0 56-59 isbpe15 in1 28-31 in0 60-63 table 2-23 specification of the time-slot quadruplet controlled by each bit in uisbper, in the different work modes of the pediu (contd) uisbper bit mode 0/1/2 mode 3/4 input stream time-slots input stream time-slots peb 20560 functional block description semiconductor group 2-103 1997-11-01 reading uisbper is standard, and accomplished by a dsp read instruction from address 0xc104. the bit sequence in the read word will be the same as in uisbper. 2.8.2.4 pediu output stream bypass enable register (uosbper) uosbper functions exactly like uisbper, except that it controls the output streams instead of the input streams. it is also a 16 bit register. each bit in uisbper determines whether a sequential quadruplet of time-slots, read from the circular ram into the output streams, will bypass the linear to a-/ m -law converter, or will be converted by it. the related sequential time-slot quadruplet of each uosbper bit, and the output stream (out0 or out1) that this quadruplet belongs to, are different when pediu is in work mode 0 or 1 and when pediu is in work mode 2, as is the case in uisbper. for more details see section 2.8.2.3 . the setting and resetting method of uosbper is exactly like the one of uisbper. only the addresses are different. every 1 in the written word indicates a bit that should be set or reset, depending on the address, and every 0 indicates a bit that should not be changed. the addresses for setting and resetting of uosbper: 0xc106: set uosbper. 0xc107: reset uosbper. the address for reading uosbper is 0xc105. for each bit in uosbper : 0 convert the related sequential time-slot quadruplet from linear to a-/ m -law bite. 1 let the related sequential time-slot quadruple to bypass the linear to a-/ m -law converter. after reset all bits of uosbper are 0. table 2-24 describes which time-slot quadruplet controlled by each uosbper bit in each pediu work mode. 15 14 13 12 11 10 9 8 uosbpe15 uosbpe14 uosbpe13 uosbpe12 uosbpe11 uosbpe10 uosbpe9 uosbpe8 76543210 uosbpe7 uosbpe6 uosbpe5 uosbpe4 uosbpe3 uosbpe2 uosbpe1 uosbpe0 peb 20560 functional block description semiconductor group 2-104 1997-11-01 the bit sequence in the read word will be the same as in uosbper. 2.8.2.5 pediu tri-state register (utsr) this 16-bit register determines the selection of output stream time-slots of every frame in which the pediu will or will not drive the du0 (data upstream input) of elic0 and du1 of elic1. the time-slots in which the pediu does not drive du-lines give external iom-2-devices the opportunity to drive these lines. each bit in utsr controls whether the pediu will drive the du-lines during quadruplet of 4 sequential time-slots. during its related time-slot quadruplet, every such bit is driven into the iom-2-mux, where it controls which unit the du-lines will be driven by. the related sequential time-slot quadruplet of each utsr bit and the output stream that this quadruplet belongs to (out0 or out1) are different when pediu is in work mode 0 or 1 than when pediu is in work mode 2 - as in uisbper and uosbper. for more details see section 2.8.2.3 . table 2-24 specification of the time-slot quadruplet that controlled by each bit in uosbper, in the different work modes of the pediu uosbper bit mode 0/1/2 mode 3/4 output stream time-slots output stream time-slots osbpe0 out0 0-3 out0 0-3 osbpe1 out0 4-7 out0 4-7 osbpe2 out0 8-11 out0 8-11 osbpe3 out0 12-15 out0 12-15 osbpe4 out0 16-19 out0 16-19 osbpe5 out0 20-23 out0 20-23 osbpe6 out0 24-27 out0 24-27 osbpe7 out0 28-31 out0 28-31 osbpe8 out1 0-3 out0 32-35 osbpe9 out1 4-7 out0 36-39 osbpe10 out1 8-11 out0 40-43 osbpe11 out1 12-15 out0 44-47 osbpe12 out1 16-19 out0 48-51 osbpe13 out1 20-23 out0 52-55 osbpe14 out1 24-27 out0 56-59 osbpe15 out1 28-31 out0 60-63 peb 20560 functional block description semiconductor group 2-105 1997-11-01 table 2-25 describes which time-slot quadruplet is controlled by each uosbper bit in each pediu work mode. the setting and resetting methods of utsr are exactly like those of uisbper and uosber; only the addresses are different. every 1 in the written word indicates a bit that should be set or reset, depending on the address, and every 0 indicates a bit that should not be changed. the addresses for setting and resetting of utsr: 0xc108: set utsr. 0xc109: resetet utsr. the address for reading utsr is 0xc10a. for each bit in utsr : 0 the pediu does not drive the related du-line (elic0-du0 or elic1-du1) during the related sequential quadruplet of time-slots. 1 the pediu drives the related du-line (elic0-du0 or elic1-du1) during the related sequential quadruplet of time-slots. the bit sequence in the read word will be the same as in utsr. after reset all bits of utsr are 0. bit 15 0 utsr ts15 ts14 ts13 ts12 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 table 2-25 specification of the time-slot quadruplet controlled by each bit in uosbper, in the different work modes of the pediu utsr bit mode 0/1/2 mode 3/4 output stream time-slots output stream time-slots ts0 out0 0-3 out0 0-3 ts1 out0 4-7 out0 4-7 ts2 out0 8-11 out0 8-11 ts3 out0 12-15 out0 12-15 ts4 out0 16-19 out0 16-19 ts5 out0 20-23 out0 20-23 ts6 out0 24-27 out0 24-27 ts7 out0 28-31 out0 28-31 ts8 out1 0-3 out0 32-35 ts9 out1 4-7 out0 36-39 peb 20560 functional block description semiconductor group 2-106 1997-11-01 2.8.2.6 pediu rom test address register (uprtar) and pediu rom test data register (uprtdr) the function of these two registers is to enable efficient testing of the pediu rom. this is a 512 word rom (9 bit address), and it holds linear values of all 8 bits a-law values and 8-bits m -low values. accessing uprtar and uprtdr is possible only when the pediu is in work mode 5 - testing mode. in this mode the input streams into the pediu are not handled by it, so accessing the pediu rom via these test registers is enabled. reading of a pediu rom content is accomplished by writing the 8 lsbs of the demanded address into uprtar, and then reading the 16 bit rom linear content from uprtdr. the msb of the rom address is the amul bit of register ucr (see section 2.8.2.1 ). this bit also determines which part of the rom is being tested - the a-law segment (0) or the m -low segment (1). address off uprtar for read and write: 0xc10b. * - written as dont care and read as 0. ta70 test address 8 least significant bits. the most significant bit is determined by the bit ucr:amul (see section 2.8.2.1 ). address off uprtdr for read only: 0xc10c. ts10 out1 8-11 out0 40-43 ts11 out1 12-15 out0 44-47 ts12 out1 16-19 out0 48-51 ts13 out1 20-23 out0 52-55 ts14 out1 24-27 out0 56-59 ts15 out1 28-31 out0 60-63 bit 15 0 uprtar ******** ta7ta0 bit 15 0 uprtdr td15td0 table 2-25 specification of the time-slot quadruplet controlled by each bit in uosbper, in the different work modes of the pediu (contd) utsr bit mode 0/1/2 mode 3/4 output stream time-slots output stream time-slots peb 20560 functional block description semiconductor group 2-107 1997-11-01 td150 test data. the pediu rom content, which its address is consist of uprtar:ta70, as the lsbs, and from ucr:amul, as the msb. note: after writing an address to uprtar, at least 1 cycle should pass before trying to read the content of this address from uprtdr. a nop can be placed between the write and read instructions, in order to sustain it. 2.8.3 pediu synchronization and clock rates 2.8.3.1 pediu synchronization by fsc and dcl the sampling of elic0-dd0, elic1-dd1 and driving elic0-du0, elic1-du1 by the pediu must be synchronized to dcl and fsc. these two signals can be inputs to the doc, or can be driven by elic0 or elic1, or by the docs internal clocks generator. the pediu is designed to sample elic0-dd0 and elic1-dd1 in falling edges of dcl: ? in work mode 0 (iom-2), dcl is a double data-rate clock, and the pediu samples the dd signals every second dcl falling edge. ? in work modes 1, 2, 3 and 4 the sampling occurs every dcl falling edge. ? in order to make the dd-signals sampling work correctly under these conditions, the elics cfi ports must transmit at dcl rising edge. ? the transmission of the next bit on elic0-du0 and/or on elic1-du1 by the pediu is done every rising edge of dcl: ? in work mode 0 the transmission occurs every second dcl rising edge ? in order to make the elics sample the du-lines correctly, the elics cfi ports must be programmed to sample the du signals at dcl falling edge. the pediu synchronizes its sampling of dd-lines and transmission on du-lines by fsc and dcl. this is done according to iom-2 specifications, similarly to the way in which the quat-s does it (see spec of the quat-s, peb 2084 version 1.2, data sheet 07.95, figures 33 and 34 at pages 64-65): ? when working in pediu work mode 0 (double data rate dcl), pediu samples the first bit of a frame at the first falling edge of dcl after dcl falling edge, in which active fsc was sampled, and the next samples occur every second dcl falling edge. ? when working in pediu work modes 1-4 (single data rate dcl), pediu samples the first bit of a frame at the same dcl falling edge, in which active fsc was sampled, every rising edge sampling of fsc by the pediu starts a new pediu frame, and resets its bit-counter and its time-slot counter. reset of these counters will occur, even if the fsc is not synchronized to the end of the former frame. in cases where the fsc rising edge sampling is too soon and occurs before the end of the frame, the counters will be reset, and the pediu starts a new frame. in such cases the output streams, which drive the up streams into the elic, will not be defined during the first time-slot of the new frame. in cases where the fsc rising edge sampling is too late, and comes after the end peb 20560 functional block description semiconductor group 2-108 1997-11-01 of the last frame, the pediu will go into idle state, from the last frame end until the fsc rising edge sampling. 2.8.3.2 restrictions on pediu clock rates the pediu should synchronize fsc dcl and input data streams (down-streams) to the dsp 2-phase system clock. the dsp clock rate can be 20 mhz, 30 mhz, or 40 mhz: ? when working with dcl rate of 4.096 mhz, the pediu will work correctly with any of these dsp rates. ? when working with dcl rate of 8.192 mhz, the dsp rate is restricted to 40 mhz. 2.8.4 pediu address space the pediu address space includes 2 address sub-spaces: ? the pediu-ram (circular-buffer) address space ? the pediu register address space. the pediu distinguishes between accesses to these two sub-spaces by 4 signals, which come from the dcl: ? read and write signals to the ram space ? read and write signals to the register space accesses of dsp to the register space will be done immediately without any wait states. during dsp accesses to the ram address space, some wait states might be necessary, when the pediu dma accesses the ram at the same time. the pediu-ram address-space in the dsp address space is between the addresses: 0xf000 - 0xf3ff. the value in the 8 lsbs define the shift in the pediu ram. the pediu register space in the dsp address space is between the addresses: 0xc100 - 0xc10f. table 2-26 specifies the use of each address in this space. table 2-26 pediu registers addresses in the dsp address space address use c100 h read and write ucr c101 h read and write usr c102 h set uisbper c103 h reset uisbper c104 h read uisbper c105 h read uosbper c106 h set uosbper c107 h reset uosbper c108 h set utsr peb 20560 functional block description semiconductor group 2-109 1997-11-01 2.8.5 pediu data processing this section describes the way in which the pediu should receive and transmit data. 2.8.5.1 pediu serial data processing the mode field of ucr defines the following: ? the length of each frame in time-slots is defined by ucr:m. ? the internal structure of each time-slot can not be changed. in all modes each time-slot is constructed from sequential 8 bits, when their sequence is from msb to lsb. the first bit of each transmitted or received time-slot is always bit 7, and the last is bit 0. transmitted time-slot form the pediu into the out streams: received time-slot by the pediu from the in streams: 2.8.5.2 pediu parallel data processing the pediu converts the received serial data into parallel data, and writes it into the pediu ram in the following manner: c109 h reset utsr c10a h read utsr c10b h read and write uprtar c10c h read uprtdr c10d h reserved c10e h reserved c10f h reserved out stream <-- bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) <---- in stream table 2-26 pediu registers addresses in the dsp address space (contd) address use peb 20560 functional block description semiconductor group 2-110 1997-11-01 ? if the written data is a linear word which was generated by a-law decoding, this word will be stored in the 13 msbs. the 3 lsbs will be 0. ? if the written data is a linear word which was generated by m -law decoding, it will be stored in the 14 msbs.the 2 lsbs will be 0 ? if the data bypassed the a-/ m -law to linear converter, it will be stored in the most significant byte (8 msbs). the 8 lsbs will be 0. the same rules are valid also when the pediu handles words, which were written to the pediu ram by the dsp. data should be stored in the following manner: ? linear data which should be encoded according to a-law should be stored in the 13 msbs, by the dsp. the 3 lsbs should be dont care. ? linear data which should be encoded according to m -law should be stored in the 14 msbs.the 2 lsbs will be 0 ? data which should bypass the linear to a-/ m -law converter should be stored in the most significant byte. the 8 lsbs are dont care bit1514131211109876543210 a-law 13 bit signed data 0 0 0 bit1514131211109876543210 m -law 14 bit signed data 0 0 bit1514131211109876543210 bypass data xxxxxxxx bit1514131211109876543210 a-law 13 bit signed data x x x bit1514131211109876543210 m -law 14 bit signed data x x bit1514131211109876543210 bypass data xxxxxxxx peb 20560 functional block description semiconductor group 2-111 1997-11-01 2.8.5.3 the circular buffer address method as can be seen in table 2-22 and in figure 2-42 , the block structure of the circular buffer is different in each mode. section 2.8.2.2 includes a description of which circular buffer blocks the pediu should access to, and which blocks should be accessed by the dsp, according to the mode and current block (cb) signal. a special method is used to simplify the dsp access to the circular buffer, during regular work of the pediu (when the pediu is active and in mode 0, 1, 2, 3 or 4). according to this method, dsp sw access to the circular buffer should not be aware the value of current block (cb) signal, or the correct circular buffer blocks to which the dsp should access during the current frame: ? for any dsp access to the circular buffer, the most significant byte of the address should be f0 h . ? the decoding of the least significant byte of the address is different in each mode, and during write operation or read operation to/from the circular buffer. circular-buffer write/read address in modes 0, 1 and 2 in modes 0, 1, 2 the circular buffer is divided into 4 in blocks and 4 out blocksC32 words each. this is shown in table 2-22 and figure 2-42 . when working in one of these modes, decoding of circular buffer write address is described as follows: index40 this field defines the index of the specific word in a 32 words circular-buffer block. stream 0/1 0 = stream 0 1 = stream 1 this field defines if the access is to a block of out-stream 0 (dsp-out0-0, dsp-out0-1) or of out-stream 1 (dsp-out1-0 or dsp-out1-1). bit 7, bit 5 these should always be 1 during a write operation. when working in modes 0-2, decoding of circular buffer read address is as follows: bit 15 14 13 12 11 10 9 8 1 1 1 1 0 0 0 0 bit76543210 1 stream 0/1 1 index (4) index (3) index (2) index (1) index (0) bit 15 14 13 12 11 10 9 8 1 1 1 1 0 0 0 0 peb 20560 functional block description semiconductor group 2-112 1997-11-01 index40 this field defines the index of the specific word in a 32 words circular-buffer block. stream 0/1 0 = stream 0 1 = stream 1 this field defines if the access is to a block of in-stream 0 (dsp-in0-0, dsp-in0-1) or of in-stream 1 (dsp-in1-0, dsp-in1-1). bits 7:5 these should always be 0 during a read operation. bits 15:8 these should contain the prefix of the circular buffer: f0 h . the pediu gets only the 8 lsbs of the address (dxap70). in order to access the correct word in the circular buffer, the pediu converts the 7 lsbs of the address into an 8 bits address. for write operation the conversion is as follows: bit 7 this is always 1 during a write operation stream0/1 this field is shifted to bit 6 cb current block (cb ) signal negation is inserted as bit 5. cb is used here because the pediu uses cb signal for its own accesses to the circular buffer. therefore, in order to access the other blocks during dsp accesses, cb must be used.for read operation the conversion is as follows: bit 7 this is always 0 during a read operation. stream0/1 this field is shifted to bit 6. cb current block (cb ) signal negation is inserted as bit 5. cb is used here because the pediu uses cb signal for its own accesses to the circular buffer. therefore, in order to access the other blocks during dsp accesses, cb must be used. bit76543210 0 stream 0/1 0 index (4) index (3) index (2) index (1) index (0) bit76 543210 dsp 1 stream0/1 cb index(4) index(3) index(2) index(1) index(0) bit76 543210 dsp 0 stream0/1 cb index(4) index(3) index(2) index(1) index(0) peb 20560 functional block description semiconductor group 2-113 1997-11-01 circular-buffer write/read address in modes 3, 4 in modes 3, 4 the circular buffer is divided into 2 in blocks and 2 out blocks C 64 words each. this is depicted in table 2-22 and figure 2-42 . when working in one of these modes the decoding of circular buffer write address is as follows: index50 the stream0/1 field is not required here, because in modes 3 and 4 only stream 0 (in0 and out0) is active. instead, the index field is 6 bits wide, because each circular-buffer block is of 64 words in modes 3 and 4. bits 7:6 these are always 1 during a write operation. when working in one of these modes the decoding of circular buffer read address is as follows: bits 7:6 these are always 0 during a write operation. the pediu gets only the 8 lsbs of the address (dxap70). in order to access the correct word in the circular buffer, the pediu converts the 7 lsbs of the address into an 8 bits address. circular-buffer converted write address in modes 3, 4: bit 7 is 1. circular-buffer converted read address in modes 3, 4: bit 15 14 13 12 11 10 9 8 1 1 1 1 0 0 0 0 bit76543210 1 1 index (5) index (4) index (3) index (2) index (1) index (0) bit 15 14 13 12 11 10 9 8 1 1 1 1 0 0 0 0 bit76543210 0 0 index (5) index (4) index (3) index (2) index (1) index (0) bit76543210 dsp 1 cb index(5) index(4) index(3) index(2) index(1) index(0) bit76543210 dsp 0 cb index(5) index(4) index(3) index(2) index(1) index(0) peb 20560 functional block description semiconductor group 2-114 1997-11-01 circular-buffer converted read address in modes 3, 4: bit 7 is 0. circular-buffer write/read address in mode 5 mode 5 is a test mode for testing the pediu rom and the pediu ram (circular buffer). in this mode the dsp can access any address of the circular buffer without any limitations for read or write operation. the internal circular-buffer address, in this mode, is the 8 lsbs of dxap (dxap70) without any conversion, and it can be any address from 0 to ff h . here, also, bits 158 of the dsp address should contain the prefix of the circular buffer: f0 h . 2.8.6 a-/ m -law conversion in voice systems, two companding/expanding laws are used: ? m -law following the bell specification is used in usa, canada, japan and philippines, ? a-law following the ccitt specification is used in europe and in other countries. the doc supports both conversion techniques by an integrated hardware logic. this hardware logic is a part of the pediu, and enables conversion from linear to a-/ m -law and from a-/ m -law to linear. this section specifies the a-/ m -law coding/decoding, as they are implemented in the doc, within the pediu. in both, a-law and m -law, the 8 bit digital code (the logarithmic data) has a sign-bit, p, three bits of segment, s2s1s0, and 4 bits, q3q2q1q0, for step selection within the chosen segment. in m -law, the 8 bit digital code is encoded/decoded from/to a 14 bit linear data, when the msb is the sign-bit. since the oak (dsp) data word is 16 bit long, these 14 bit are inserted in the 14 msbs:. in a-law, the 8 bit digital code is encoded/decoded from/to a 13 bit linear data, when the msb is the sign-bit. since the oak (dsp) data word is 16 bit long, these 13 bit are inserted in the 13 msbs:. bit76543210 p s2 s1 s1q3q2q1q0 bit1514131211109876543210 m -law 14 bit signed data 0 0 bit1514131211109876543210 a-law 13 bit signed data 0 0 0 peb 20560 functional block description semiconductor group 2-115 1997-11-01 2.9 on-chip emulation (ocem) the on-chip emulation (debugger) allows bugs in the application software to be found and corrected early in design cycle. it is implemented partly in hardware and partly in software. it interprets functions such as go, abort, stop, data read/write and also performes instruction and data breakpoints, program flow trace buffering and breakpoint on event at operation cycle speed without additional off-chip hardware. different breakpoints can be set on: ? program address ? data address ? data value ? single step ? interrupt once a condition is met the on-chip emulation activates the trap mechanism causing the kernel to suspend any action and jump into the service routine. an additional external signal (stop pin) is provided to stop in parallel any connected processing element. program flow tracing includes dynamic recording of program addresses. those addresses provide a full program flow graph of instruction being executed. 2.10 mailbox the m p and the dsp communicate via a bidirectional mailbox according to a user definable protocol. this mailbox includes two separate parts: ? m p mailbox - enables transfer from the m p to the oak. ? oak mailbox - enable transfer from the oak to the m p. both parts includes a command register, 6 16 bits registers and a busy bit. the commands syntax will be defined by the user. an example for some commands can be found in the boot sequence definition within the dcu description. 2.10.1 m p mailbox the m p mailbox includes six general purpose sixteen bit registers (mdtx), an 8-bit command register (mcmd) and one 8-bit busy register (mbusy). the registers mdtx and mcmd can be written by the m p and read by the oak. mbusy can be read by m p. a write of the m p to the m p mailbox command register generates an interrupt to the oak (int2). therefore, when the user wants to transfer more data the command register must be written last. a busy bit which can be read by the m p (mbusy) is set automatically after a write to the m p command register and reset by a direct oak write operation to it. users can define own opcodes (up to 256 opcodes) for the transfer direction from the m p to the oak. peb 20560 functional block description semiconductor group 2-116 1997-11-01 data transfer from the m p to the oak ? the m p tests the mbusy bit. ? the m p writes to the data registers (optional). ? the m p writes to the m p-command register (mcmd) (must be performed) - this write sets automatically the m p mailbox busy bit (mbusy). ? an oak interrupt (int2) is activated due to the write to the command register. ? the oak int2 routine reads mcmd and performs the command (the read of the command register stops the int2 activation automatically). ? if the command is asking for data (like a read of an oak register), the interrupt routine puts the data in the oak mailbox registers. ? when finished, the int2 routine resets mbusy for enabling the m p to send the next command. the m p can write consecutive writes to the m p mailbox and its up to the user to make sure that the data has been transferred to the oak correctly (the busy bit has been reset) before writing new data to the m p mailbox. 2.10.2 oak mailbox the oak mailbox includes: ? six general purpose 16-bit registers (odtx) ? an 8-bit command register (ocmd) ? one bit busy register (obusy). all the registers can be written by the oak and read by the m p. a write of the oak to the oak mailbox command register generates an interrupt to the m p (int source no.6). therefore, when the user wants to transfer more data then the command register must be written last. a busy bit (obusy) which can be read by the oak is set automatically after a write of the oak to the oak command register and is reset by a direct m p write to it (when the m p has finished reading the oak mail box contents). users can define own opcodes (up to 256 opcodes) for the transfer direction from the oak to the m p. data transfer from the oak to the m p ? the oak tests the obusy bit. ? the oak writes to the data registers (optional). ? the oak writes to the command register (ocmd) (must be performed). this write operation sets the oak mailbox busy bit (obusy). ?a m p interrupt is activated due to the write operation to the command register. ? the m p reads the command register and performs the command. ? if the command is asking for data (like a read of a m p register), the interrupt routine puts the data in the m p mailbox registers. peb 20560 functional block description semiconductor group 2-117 1997-11-01 ? when finished, the m p resets obusy bit for enabling the oak to send the next command. this operation also deactivates the m p-mailbox interrupt. note: 1) the obusy bit is set only 4 dsp cycles after a oak write operation to ocmd register. therefore, the first polling-read cycle of obusyr should take place at least 5 dsp clock cycles after the write cycle to ocmd. 2) the oak can write consecutive writes to the oak mailbox and its up to the user to make sure that the data has been transferred to the m p correctly (obusy has been reset) before writing new data to the oak mailbox . note: the busy bit within mbusyr and obusyr is always read or written at the msb. table 2-27 register contents register description reset value bit oak access m p access m p add. for msb m p add for lsb oak addr. mcmd m p command 00h 8 r w none 340 h c040 h mbusyr m p mb busy 0h 1 w r none 341 h c041 h mdt0 m p data reg 0 un-changed 16 r w 343 h 342 h c042 h mdt1 m p data reg 1 un-changed 16 r w 345 h 344 h c044 h mdt2 m p data reg 1 un-changed 16 r w 347 h 346 h c046 h mdt3 m p data reg 1 un-changed 16 r w 349 h 348 h c048 h mdt4 m p data reg 1 un-changed 16 r w 34b h 34a h c04a h mdt5 m p data reg 1 un-changed 16 r w 34d h 34c h c04c h ocmd oak command 00h 8 w r none 350 h c050 h obusyr oak mb busy 0h 1 r w none 351 h c051 h odt0 oak data reg 0 un-changed 16 w r 353 h 352 h c052 h odt1 oak data reg 1 un-changed 16 w r 355 h 354 h c054 h odt2 oak data reg 2 un-changed 16 w r 357 h 356 h c056 h odt3 oak data reg 3 un-changed 16 w r 359 h 358 h c058 h odt4 oak data reg 4 un-changed 16 w r 35b h 35a h c05a h odt5 oak data reg 5 un-changed 16 w r 35d h 35c h c05c h peb 20560 functional block description semiconductor group 2-118 1997-11-01 oak reads of address c051 h will therefore result with: note: the obusy bit is set only 4 dsp cycles after a oak write operation to ocmd register. therefore, the first polling-read cycle of obusyr should take place at least 5 dsp clock cycles after the write cycle to ocmd. m p read of address 341 h will result with : 2.11 m p interface the system data interface is a passive interface adaptable to different microprocessor bus schemes: ? 8-bit data bus multiplexed with lower 8 bits of the address bus ? upper address bus for an access to all accessible doc registers. ? control lines 2.11.1 compatibility the bus is compatible to the following types of m ps: ? siemens c16x ? intel 80x86/88 or note: in 32-bit m p systems (e.g. based on i80386, m68xxx or mipc r3000), an external logic for control signals generation is necessary (e.g. sequencer pals). 2.11.2 memory and i/o organization the doc is a slave to the microprocessor. the m p can access all doc registers but the dsp memory, the dsp registers, the dsp memory mapped registers and the pediu. the m p can communicate with the dsp via the m p mailbox only. for more details see register overview, section 5.1 . bit 15 14131211109876543210 obusyr obusy 000000000000000 bit 7 6543210 mbusyr mbusy 0000000 peb 20560 functional block description semiconductor group 2-119 1997-11-01 2.12 clock generator an integrated clock generator provides all required clocking frequencies. 2.12.1 block diagram figure 2-45 doc clock generator its10099 30.72 mhz clk30 15.36 mhz clk15 7.68 mhz clk7 mux 50% osc dsp clk 61.44 mhz x0 osc 40 mhz clk61 clk40-xi -xo lowpass osc 16.384 mhz vcxo clk16 v vcxo 512 khz mux xclk refclk refs rtc 8 khz 1 hz 100 hz 10 ms int rtclk 1 s 2048 khz 1536 or 512 or 8 or phase comparator mux mux 8.192 mhz m/s pdc8-i pdc8-o m/s pdc4-i pdc4-o mux 4.096 mhz pdc2-o pdc2-i m/s 2.048 mhz mux pfs-o pfs-i m/s 512 khz mux m s ~1 1.024 mhz 8 khz doc 2 2 2 3 2 2 15 64 8000 80 2 2 2 4 64 3 4 512 khz peb 20560 functional block description semiconductor group 2-120 1997-11-01 2.12.2 types of clock signals 2.12.2.1 input/output clocks ? clk16: 16.384 mhz vcxo clock voltage oscillator input ? clk61: 61.44 mhz ext. oscillator clock input ? clk40-xi: up to 40 mhz ext quartz clock input ? clk40-xo: up to 40 mhz ext quartz clock output ? clk30: 30.72 mhz (i.e. for m p) output ? clk15: 15.36 mhz (i.e. for octat-p) output ? clk7: 7.68 mhz (i.e. for quat-s) output ? pfs: frame synchronization on pcm 8 khz input/output ? pdc2: pcm data clock 2.048 mhz input/output ? pdc4: pcm data clock 4.096 mhz input/output ? pdc8: pcm data clock 8.192 mhz (i.e. for falc54) input/output ? fsc: frame synchronization on iom-2 interface 8 khz input/output ? dcl: iom-2 data clock input/output ? xclk: 8 khz or 512 khz or 1.536 mhz or 2.048 mhz (selectable) input ? refclk (i.e. 512 khz) input/output 2.12.2.2 clock selection ? dsp clock: selectable clock ~ 20, 30 or 40 mhz internal clock C the dsp clock can be selected from 3 possible frequencies: 20, 30 or 40 mhz. C the source of the clock can be one of two: 61.44 mhz external oscillator, which by dividing by 2,3 produces the 20, 30 mhz clock 40 mhz crystal with an internal oscillator which produces the 40 mhz clock. C dsp clock frequency is determined by the input pins, freq10. the value of these pins can be read from ccsel0 register, bits10 (read only bits). ? rtclk: real time clock C clock for real time interrupt: 1 hz (1 s) or 100 hz (10 ms) internal clock C the rtc interrupt is a periodic interrupt activated every 10 ms/1 s and it is programmable via ccsel1:rtcp. ? programmable uart clock internal clock C the uart clock is clk61 divided by 5. it can be further divided by programming the uart. (for more details see table 2-34 in section 2.14.1.2 ) ? pfs: frame synchronization on pcm 8 khz input/output C the pfs signal can be derived from either the clk16 input clock or be driven by an external signal via the io pads. the selection between external and internal signals is performed by ccsel0:ms (master/slave bit). see figure 2-46 . peb 20560 functional block description semiconductor group 2-121 1997-11-01 figure 2-46 pfs signal selection ? elic0 and elic1 pcm interface clocks: internal clocks C elic0 and elic1 receive the same pdc and pfs clocks. C pdc has 3 optional frequencies: 2.048 mhz, 4.096 mhz and 8.192 mhz, which are produced from the 16.384 mhz input clock or driven by external clocks via io pads. see figure 2-47 . C for correct functionality, the pdc frequency must be selected according to the elics operation mode. C both elics are connected to the same pdc. C pdc frequency and configuration are determined by register ccsel0 bits 42. during reset, pdc frequency is driven from an internal 8.192 mhz clock. no pdc will be driven on io (even though cclse0[4] =1) before ccsel0 is written. C the selected pdc functions as the elic0 watch-dog timer clock, which also serves as the doc watch-dog timer (the elic1 watch-dog timer exists but unused). its10100 clk 16:8 mux ccsel[4] note: pfs is doc's input pin. pfs elic r pfs 4 64 peb 20560 functional block description semiconductor group 2-122 1997-11-01 figure 2-47 pdc generation ? iom-2 interface selected fsc clock input/output C the fsc signal can be selected from driven by 3 sources: output: fsc produced by elic0 (derived from the selected pfs clock, internally, in elic0). fsc drives the output signal. (elic0:cmd1:css = 0) note: in this case elic1 should be programmed to produce its own internal fsc even though it has no effect beyond the elic1 block. elic0:cmd1:css and elic1:cmd1:css must be programmed with the same value. input: fsc driven by io ((elic0:cmd1:css = 1) and (ccsel1[0] = 1)) output: fsc driven by selected pfs ((elic0:cmd1:css = 1) and (ccsel1[0] = 0)) ? iom-2 interface selected dcl clock input/output C the dcl signal can be selected from 3 sources: output: dcl produced by elic0; derived from the selected pdc clock; drives the output signal. (elic0:cmd1:css = 0) note: in this case elic1 should be programmed to produce its own internal dcl even though it has no effect beyond the elic1 block. elic0:cmd1:css and elic1:cmd1:css must be programmed with the same value. its10101 clk 16 mux note: pdc2/4/8 are doc's input signals. mux mux mux ccsel0[2,3] ccsel0[4] (m/s) pdc 2 pdc 4 pdc 8 elics pdc 2 2 2 peb 20560 functional block description semiconductor group 2-123 1997-11-01 input: dcl driven by io ((elic0:cmd1:css = 1) and (ccsel1[2] = 1)) output: dcl driven by selected pdc (pdc4, pdc8). ((elic0:cmd1:css = 1) and (ccsel1[2] = 0)) pdc4, 8 can be inputs or outputs, depends if the doc is master or slave. note : when dcl is input or driven directly from pdc4/8, it should be used as an input by elic0 and elic1. ? sacco-b0 input clocks internal clocks C there are two sacco-b0 clocks, hfs and hdc. each one may be selected from several possible sources as sacco-b0 can be connected to the iom signaling mux, to the pcm signaling mux or directly to the io when in stand-alone mode. C hfs: hfs sources: port3/hfsb0 input pin, when disconnected from both pcm and iom signaling muxes. fsc, when sacco-b0 is connected to the iom signaling mux. pfs, when sacco-b0 is connected to the pcm signaling mux. C hdc: hdc sources: pdc2, pdc4, pdc8, dcl C when disconnected from both signaling muxes (ccsel1[5:4]). each of these signals can be an inputs or an outputs, according to the configuration. pdc when sacco-b0 is connected to the pcm signaling mux. dcl when sacco-b0 is connected to the iom signaling mux. ? sacco-b1 clocks internal clocks C there are two sacco-b1 clocks, hfs and hdc. each one may be selected from several possible sources, as sacco-b1 can be connected to the iom signaling mux, to the pcm signaling mux or directly to the io when in stand-alone mode. C hfs: hfs sources: du5/hfsb1 input pin C when disconnected from both signaling muxes. fsc when sacco-b1 is connected to the iom signaling mux. pfs when sacco-b1 is connected to the pcm signaling mux. C hdc: hdc sources: pdc2,pdc4,pdc8,dcl0 C when disconnected from both signaling muxes (ccsel1[7:6]). each of these signals can be inputs or outputs, according to the configuration. pdc when sacco-b1 is connected to the pcm signaling mux. dcl when sacco-b1 is connected to the iom signaling mux. ? sidec clocks internal clocks C the sidec module includes four hdlc controllers. each one receives hdc and hfs clocksfrom the iom-2 interface. C the hdc clocks are driven by dcl. peb 20560 functional block description semiconductor group 2-124 1997-11-01 C the hfs clocks are driven by fsc. ? pediu clocks internal clocks C data clock is driven by iom-2 interface selected dcl C frame clock is driven by iom-2 interface selected fsc ? clock for run time statistics: 1.024 mhz (~ 1 m s) internal clock C the run time statistics pulse is a periodic clock toggling at 1.024 mhz. it is derived from the clk16 input clock and is used in dcu for dsp statistics. ? sacco-a0 input clocks: internal clocks C there are two sacco-a0 clocks, hfs and hdc. these clocks can be provided only, internally, by elic0. (only clock mode 3 of sacco-a0 is available.) ? sacco-a1 input clocks: internal clocks C there are two sacco-a1 clocks, hfs and hdc. these clocks can be provided only, internally, by elic1. (only clock mode 3 of sacco-a1 is available.) peb 20560 functional block description semiconductor group 2-125 1997-11-01 2.12.3 clocks generator registers description 2.12.3.1 clocks select 0 register (ccsel0) address: 360 h m p interface mode: read/write reset value: 0001_00xx - where xx depends on input pins. note: bits 10 are read only bits 7 5 are unused, and are read as 0. this register fulfils the following functions: ? dsp frequency indication. ? pcm data clock (pdc) frequency selection. ? definition if the doc functions as pcm clocks master (pdc and pfs generator) or as pcm clocks slave (the doc gets pdc and pfs, as inputs). dspf10 dsp frequency 00: 20 mhz 01: 30 mhz 10: 40 mhz 11: 61 mhz (used only for testing) note: these bits are read only, and there value is determined by the input pins: frq10. pdcf10 pdc frequency for elic0 and elic1 00: 8.192 mhz 01: 4.096 mhz 10: 2.048 mhz 11: reserved ms master/slave (pdc & pfs internal/external) 0: slave - pdc and pfs are external. 1: master - pdc and pfs are internal and driven on io note: after reset, pdc/pfs are internally by the clocks generator, but the pdc/pfs pins stay in tri-state. pdc/pfs are driven by the doc, only after the first write access to ccsel0, if the doc was configured as master. bit 7 bit 0 0 0 0 ms pdcf1 pdcf0 dspf1 dspf0 peb 20560 functional block description semiconductor group 2-126 1997-11-01 2.12.3.2 clocks select 1 register (ccsel1) address: 361 h m p interface mode: read/write reset value: 00 h this register fulfils the following functions: ? iom-2-interface-dcl source and frequency. ? iom-2-interface-fsc source. ? sacco-b0/1 hdc source when does not connected to any of the signaling muxes. ? real time clock interrupt period. sb1dc10 sacco-b1 hdc selection select sacco-b1 hdc when it does not connected to pcm/iom signaling muxes. 00: select pdc8 01: select pdc4 10: select pdc2 11: select dcl0 sb0dc1 0 sacco-b0 hdc selection select sacco-b0 hdc when it does not connected to pcm/iom signaling muxes. 00: select pdc8 01: select pdc4 10: select pdc2 11: select dcl0 rtcp real time clock interrupt period 0: 10ms period 1: 1 s period dcls iom-2 interface data clock select dcl from io/pdc (see the note at the end of this section) 0: dcl from pdc (dcl pin is used as an output) 1: dcl from io (dcl pin is used as an input) dclf - iom2 interface data clock frequency. select dcl from pdc4/pdc8 (valid only when dcls = 0) 0: dcl is pdc8 1: dcl is pdc4 bit 7 bit 0 sb1dc1 sb1dc0 sb0dc1 sb0dc0 rtcp dcls dclf fscs peb 20560 functional block description semiconductor group 2-127 1997-11-01 fscs - iom2 interface frame synchronization clock select. select fsc from io/pfs. 0: fsc from pfs 1: fsc from io note: 1) although the fsc/dsl ports are tri-state after reset, fsc/dcl are driven internally by the input signal clk16 divided by 2 for dcl, by 2048 for fsc. fsc pin is driven by the doc, only after write access to ccsel1, if fsc was configured as an output. 2) bits 0,2 are valid only when elic0:cmd1:css = 1 (internal elic0 gets fsc and dcl as inputs). 3) after reset elic0:css=0 (internal elic provides dcl, fsc), therefore dcls and fscs should be set to 1. otherwise (if programmed to 0) the internal pdc (8 mhz), pfs (8 khz) are output on dcl/fsc until the cfi interface is enabled (elic0:omdr:csb=1). the result would be unpredictable behavior of the connected layer 1 devices. 4) bits 0 and 2 should be programmed to the same value to ensure the correct functionality of the doc. peb 20560 functional block description semiconductor group 2-128 1997-11-01 2.12.3.3 clocks select 2 register (ccsel2) address: 362 h m p interface mode: read/write reset value: 00 h note: bits 76 are unused, and are read as 0. this register fulfils the following functions: ? refclk io control. ? vco frequency selection. ? reference clock source selection. ? reference clock dividor selection. rcd1 0 reference clock divider 00: no division of reference clock 01: forbidden 10: divide reference clock by 3 11: divide reference clock by 4 vcxof voltage control oscillator frequency 0: select 512 khz clock 1: select 8 khz clock rcs1 0 reference clock source 00: select internal 512 khz as reference clock 01: select refclk as reference clock 10: select xclk as reference clock 11: select internal 8 khz clock as reference clock rcdir refclk direction 0: refclk is input 1: refclk is output note: the first write access to the doc (after reset) should not be addressed to ccsel2 register. bit 7 bit 0 0 0 rcd1 rcd0 vcxof rcs1 rcs0 rcdir peb 20560 functional block description semiconductor group 2-129 1997-11-01 2.13 interrupt controller all doc interrupt sources send their interrupt request to the m p through the interrupt control unit. this unit checks if the m p allows an interrupt (ie). ? if the interrupt is not masked, the controller sends an interrupt request to the m p. as a result, the m p sends interrupt acknowledge through the iack input and the interrupt controller puts the address of the interrupt source on the m p data bus. ? interrupt acknowledge from the m p (iack ). according to the interrupt-acknowledge protocol defined by the selected m p bus mode this signal has different behavior. in siemens/intel mode the vector is driven by the falling edge of the 2nd (last) pulse of iack . in motorola mode the vector is driven by the falling edge of the 1st (and only) pulse. ? if more than one unit sends an interrupt request at the same time, the interrupt control unit sends the highest prior source interrupt request first. the m p can also read the global interrupt status register (igis). the doc version 2.1 provides two new 8-bit interrupt status registers (igis0 and igis1) for applications in which the generated interrupt vector can not be used. the pending interrupt status is displayed by reading the registers. 2.13.1 mask (imask0, imask1) each interrupt source has a bit in a mask register (imaskr). ? if the bit is 1, the interrupt is disregarded. ? if the bit is 0, the interrupt is handled interrupt mask registers (imaskr) there are two 8-bit mask registers in the doc: imaskr0 and imaskr1. value in both registers after reset: ff h interrupt mask register 0 (imaskr0) address 302 h read and write reset value ff h bit 7 0 imaskr0 m7 m6 m5 m4 m3 m2 m1 m0 peb 20560 functional block description semiconductor group 2-130 1997-11-01 interrupt mask register 1 (imaskr1) address 303 h read and write reset value 07 h m10 to m0 mask bits 0 = not masked interrupt (the interrupt is enabled) 1 = masked interrupt (the interrupt is disabled) note: after reset, all interrupts are disabled. 2.13.2 interrupt sources 2.13.3 interrupt priority (ipar0, ipar1, ipar2) all interrupt sources can be assigned by the user into four different priority groups: ? group no. 11 has the highest priority ? group no. 00 the lowest priority. the interrupt priority within the group is defined by the physical source number: ? s0 has the highest priority ? s10 has the lowest priority. bit 7 0 imaskr1 00000m10m9m8 table 2-28 interrupt sources source number interrupt sources interrupt name fixed source identifier doc address base s0 elic0 eint0p 0000 s1 elic1 eint1p 0001 s2 sidec: sacc0 s0intp 0010 s3 sidec: sacc1 s1intp 0011 s4 sidec: sacc2 s2intp 0100 s5 sidec: sacc3 s3intp 0101 s6 oak-mail box dintp 0110 s7 gpio port vintp 0111 s8 fsc uintp 1000 s9 uart aintp 1001 s10 rtc (1 s or 10 ms clk) cintp 1010 peb 20560 functional block description semiconductor group 2-131 1997-11-01 for example: s2, s3, s9 and s10 are programmed into the same priority group s2 will have highest priority. figure 2-48 priority unit - block diagram registers for priority assignment (ipar) interrupt priority assignment register 0 (ipar0) address 304 h , read and write interrupt priority assignment register 1 (ipar1) address 305 h , read and write interrupt priority assignment register 2 (ipar2) address 306 h , read and write s10 to s0 interrupt sources 11 = highest priority group 10 = second priority group 01 = third priority group 00 = lowest priority group interrupt doc address base (idoc) address 300 h , read and write bit 76543210 ipar0 s3 s2 s1 s0 bit 76543210 ipar1 s7 s6 s5 s4 bit 76543210 ipar2 s10 s9 s8 bit7430 idoc 0000 doc interrupt address base itb10102 group interrupt source interrupt request group by the placed interrupts priority manager source no ireq peb 20560 functional block description semiconductor group 2-132 1997-11-01 interrupt vector (int_vec) this is the vector which is being read during interrupt acknowledge cycle. the 8-bit vector contains a 4-bit programmable interrupt address base, which can be programmed via idoc, and a 4-bit interrupt source identifier (see table 2-28 ). 2.13.4 interrupt cascading the doc interrupt controller supports two cascading schemes which can be selected by programming the ipc register. interrupt port configuration register (ipc) reset value: 00 h m p interface mode: read/write address: 301 h note: bits 76 are unused and are read as 0. mode interrupt handling mode 0 intel scheme 1 motorola scheme sla1 0 slave address used only in slave cascading mode (refer to casm). casm cascading mode 0 slave cascading mode pins ie0, ie1 are used as inputs. interrupt acknowledge is accepted if an interrupt signal has been generated and the values on pins ie1 0 correspond to the programmed values in sla1 0 (slave address). 1 daisy chaining mode pin ie0, as interrupt enable output, and pin ie1, as interrupt enable input, are used for building a daisy chain. interrupt acknowledge is accepted if an interrupt signal has been generated and interrupt enable input, ie1, is active high during a subsequent iack cycle(s). if pin int goes active, interrupt enable output, ie0, is immediately set to low. bit7430 int_vec doc interrupt address base source identifier bit 7 0 ipc 0 0 mode sla1 sla0 casm ic1 ic0 peb 20560 functional block description semiconductor group 2-133 1997-11-01 ic1 0 interrupt port configuration these bits define the function of interrupt output level (pin int): 2.13.4.1 slave mode interrupt outputs of several devices (slaves) are connected to a priority resolving unit (i.e. interrupt controller). the slave which is selected for the interrupt service routine is addressed via special address lines during the interrupt acknowledge cycle. for this application the doc offers two interrupt enable inputs (ie0, ie1) and a programmable 2-bit slave id (in a doc register). refer to: figure 2-49 for interrupt cascading in siemens/intel bus mode. figure 2-49 interrupt cascading (slave mode) in siemens/intel bus mode table 2-29 ioc1 ioc0 function 0 0 open drain output 0 1 push/pull output, active low 1 1 push/pull output, active high 1 0 forbidden its10103 int m p 8259a doc iack ie0,1 ireq iack ie0,1 doc ireq iack ie0,1 doc ireq inta 22 2 ir5 ir4 ir0 ir6 ir7 cas0...cas2 inta int peb 20560 functional block description semiconductor group 2-134 1997-11-01 for intel type microprocessor systems the 2-cycle interrupt acknowledge scheme is supported (80x86 mode). 2.13.4.2 daisy chaining if selected via ipc register the interrupt enable pins ie0, ie1 are used for building a daisy chain by connecting the interrupt enable output (ie0) of the higher priority device to the interrupt enable input (ie1) of the lower priority device. the highest priority device has ie1 pulled high. refer to: figure 2-50 for interrupt cascading in siemens/intel bus mode. figure 2-50 interrupt cascading (daisy chaining) in siemens/intel bus mode for intel type microprocessor systems the 2-cycle interrupt acknowledge scheme is supported 80x86 mode. maximum available settling time for the chain: from the beginning of the first inta cycle to the beginning of the second. for motorola type m p systems the maximum available setting time for the chain is: from the beginning of the iack cycle to the falling edge of the rd /ds signal. refer to motorola timing, table 7-8 . its10105 int m p doc ie0 iack ireq ie0 doc ireq ie0 doc ireq inta +5 v +5 v ie1 ie1 ie1 iack iack peb 20560 functional block description semiconductor group 2-135 1997-11-01 2.13.5 global interrupt status registers (igis0 and igis1) the doc version 2.1 provides two new 8-bit interrupt status registers (igis0 and igis1) for applications in which the generated interrupt vector can not be used. the pending interrupt status is displayed by reading the registers. global interrupt status registers (igis0) address 30ah read only reset value 00h global interrupt status registers (igis1) address 30bh read only reset value 00h note: bits 73 are not used, and are read as 0. for interrupts description see the following table with interrupts sources. bit 7 0 igis0 is7 is6 is5 is4 is3 is2 is1 is0 bit 7 3 0 igis1 00000 dont care is9 dont care table 2-30 interrupt sources number interrupt status interrupt source reset control for bits in igis0 and igid1 s0 is0 elic0 read access to registers: elic0: ista, elic0-epic: ista-e, cififo elic0-saccoa: ista, exir elic0-saccob: ista, exir s1 is1 elic1 read access to registers: elic1: ista, elic1-epic: ista-e, cififo elic1-saccoa: ista, exir elic1-saccob: ista, exir s2 is2 sidec0 sidec0: ista, exir peb 20560 functional block description semiconductor group 2-136 1997-11-01 note: the fsc and rtc interrupts sources are reset by interrupt acknowledge line (iack) when the appropriate interrupt vector is driven on the data bus. the other interrupts are reset by reading from or writing to the appropriate register in the interrupt source module. thus the fsc and rtc interrupts are not supported in the pending interrupt status register. it is recommended to mask the fsc and rtc interrupts in the interrupt mask register, when working with the pending interrupt status (not using the interrupt vector). both interrupts can be generated via the m p-mailbox interrupt by the dsp software as the dsp uses fsc interrupts internally. it may also count the fsc interrupts to e.g. 1 ms and then send a message to the m p. 2.14 universal asynchronous receiver/transmitter (uart) the uart performs serial-to-parallel conversion on data characters received from a peripheral device or a modem, and parallel-to-serial conversion on data characters received from the cpu. the m p can read the complete status of the uart at any time during the functional operation. status information reported includes the type and condition of the transfer operations being performed by the uart, as well as any error condition (parity, overrun, framing, or break interrupt). the uart includes a programmable baud rate generator that is capable of dividing the timing reference clock input by 1 to (2 16 C 1), and of producing a 16 clock for driving the internal transmitter logic. provisions have also been made to use this 16 clock for driving the receiver logic. the uart features full modem-control capability and a processor-interrupt system. interrupts can be programmed to the users requirements, minimizing the computing required for handling the communications link. s3 is3 sidec1 sidec1: ista, exir s4 is4 sidec2 sidec2: ista, exir s5 is5 sidec3 sidec3: ista, exir s6 is6 oak-mail box write access to obusy s7 is7 gpio port read access vdata s8 - fsc not available (see note below) s9 is9 uart see table 2-36 on page 149 s10 - rtc not available (see note below) table 2-30 (contd) interrupt sources number interrupt status interrupt source reset control for bits in igis0 and igid1 peb 20560 functional block description semiconductor group 2-137 1997-11-01 the integrated uart is compatible to the standard 16c550a uart, figure 2-51 . it has the following features: ? receiver and transmitter are each buffered with 16-byte fifos (in the fifo mode) to reduce the number of interrupts presented to the m p ? adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data stream ? holding and shift registers eliminate the need for precise synchronization between the m p and the serial data ? independent control of transmit, receive, line status and data set interrupts ? programmable baud rate generator for 300 baud to 256 kbaud; it generates the internal 16 clock using an internal clock source. ? modem control functions (cts , rts , dsr, dtr, ri and dcd ) ? false start bit detection ? complete status reporting capabilities ? fully programmable serial-interface characteristics: C 5-, 6-, 7-, 8- bit characters C even, odd, or non-parity generation and detection C 1-, 1 -, or 2-stop bit generation C baud generation (dc to 256 kbaud) ? tri-state ttl drive capability for bidirectional data bus and control bus ? line break generation and detection ? internal diagnostic capabilities: C loopback controls for communication link fault isolation C break, parity, overrun, framing error simulation ? fully prioritized interrupt system controls peb 20560 functional block description semiconductor group 2-138 1997-11-01 figure 2-51 uart block diagram the system programmer may access any of the uart registers summarized in table 2-31 via the m p. these registers control uart operations including transmission and reception of data. each register bit in table 2-31 has its name and reset state shown in table 2-33 . itb10107 fifo receiver transmitter fifo modem control lines i/o-port multiplexer interupt control logic and control logic select data buffer bus uart internal doc bus doc rxdu txdu rts cts dcd dsr dtr ri peb 20560 functional block description semiconductor group 2-139 1997-11-01 2.14.1 registers overview table 2-31 summary of registers 1 bit no. register address 0 (dlab = 0) 0 (dlab = 0) 1 (dlab = 0) 2 2 3 receiver buffer register (read only) transmitter holding register (write only) interrupt enable register interrupt ident. register (read only) fifo control register (write only) line control register rb r th r ier iir fcr lcr 0 data bit 0 1) data bit 0 1) enable received data available interrupt (erbfi) 0 if interrupt is pending fifo enable (fewo) word length select bit 0 (wls0) 1 data bit 1 data bit 1 enable transmitter holding register empty (etbei) interrupt id bit 0 (iidb0) receiver fifo reset (rfr) word length select bit 1 (wls1) 2 data bit 2 data bit 2 enable receiver line status interrupt (erlsi) interrupt id bit 1 (iidb1) transmitter fifo reset (tfr) number of stop bits (stb) 3 data bit 3 data bit 3 enable modem status interrupt (eddssi) interrupt id bit 2 (iidb2) dma mode select (dms) parity enable (pen) 4 data bit 4 data bit 4 0 0 reserved even parity select (eps) 5 data bit 5 data bit 5 0 0 reserved stick parity (stp) peb 20560 functional block description semiconductor group 2-140 1997-11-01 6 data bit 6 data bit 6 0 fifos enabled (fe) 2) rcvr fifo trigger level (lsb) set break (sbr) 7 data bit 7 data bit 7 0 fifos enabled (fe) 2) rcvr fifo trigger level (msb) divisor latch access bit (dlab) table 2-32 summary of registers 2 bit no. register address 45 6 70 (dlab = 1) 1 (dlab = 1) modem control register line status register modem status register scratch register divisor latch (ls) divisor latch (ms) mcr lsr msr scr dll dlm 0 data terminal ready (dtr) data ready (dr) delta clear to send (dcts) bit 0 bit 0 bit 8 1 request to send (rts) overrun error (oe) delta data set ready (ddsr) bit 1 bit 1 bit 9 2 out 1 parity error (pe) trailing edge ring indicator (teri) bit 2 bit 2 bit 10 3 out 2 framing error (fe) delta data carrier detect (ddcd) bit 3 bit 3 bit 11 table 2-31 summary of registers 1 (contd) bit no. register address 0 (dlab = 0) 0 (dlab = 0) 1 (dlab = 0) 2 2 3 receiver buffer register (read only) transmitter holding register (write only) interrupt enable register interrupt ident. register (read only) fifo control register (write only) line control register rb r th r ier iir fcr lcr peb 20560 functional block description semiconductor group 2-141 1997-11-01 4 loop break interrupt (bi) clear to send (cts) bit 4 bit 4 bit 12 5 0 transmitter holding register (thre) data set ready (dsr) bit 5 bit 5 bit 13 6 0 transmitter empty (temt) ring indicator (ri) bit 6 bit 6 bit 14 7 0 error in rcvr fifo (eirf) 2) data carrier detect (dcd) bit 7 bit 7 bit 15 1) bit 0 is the least significant bit. it is the first bit serially transmitted or received. 2) these bits are always 0 in the sab 16c450 compatible mode. table 2-33 register reset values register/signal reset control reset state interrupt enable register master reset 0000 0000 1) interrupt identification register master reset 0000 0001 fifo control register master reset 0000 0000 line control register master reset 0000 0000 modem control register master reset 0000 0000 line status register master reset 0110 0000 modem status register master reset xxxx 0000 2) sout master reset high intr (rcvr errors) read lsr/mr low intr (rcvr data ready) read lsr/mr low table 2-32 summary of registers 2 (contd) bit no. register address 45 6 70 (dlab = 1) 1 (dlab = 1) modem control register line status register modem status register scratch register divisor latch (ls) divisor latch (ms) mcr lsr msr scr dll dlm peb 20560 functional block description semiconductor group 2-142 1997-11-01 uart address 2-0 address signals connected to these 3 inputs select a uart register for the m p to read from or write to during data transfer. a table of registers and their addresses is shown below. note that the state of the divisor latch access bit (dlab), which is the most significant bit of the line control register, affects the selection of certain uart registers. the dlab must be set high by the system software to access the baud rate generator divisor latches . 1) boldface bits are permanently low. 2) bits 7-4 are driven by the input signals. intr (thre) read ilr/write thr/mr low intr (modem status changes) read msr/mr low out2 master reset high rts master reset high dtr master reset high out1 master reset high rcvr fifo mr/rfr ? fewo/ d fewo all bits low xmit fifo mr/t fr ? fewo/ d fewo all bits low table 2-34 uart registers and addresses dlab a2 a1 a0 register 0 0 0 0 receiver buffer (read), transmitter holding register (write) 0 0 0 1 interrupt enable x 0 1 0 interrupt identification (read) x 0 1 0 fifo control (write) x 0 1 1 line control x 1 0 0 modem control x 1 0 1 line status x 1 1 0 modem status x 1 1 1 scratch 1 0 0 0 divisor latch (least significant byte) 1 0 0 1 divisor latch (most significant byte) table 2-33 register reset values (contd) register/signal reset control reset state peb 20560 functional block description semiconductor group 2-143 1997-11-01 2.14.1.1 line control register (lcr) the system programmer specifies the format of the asynchronous data communications exchange and sets the divisor latch access bit via the line control register (lcr). the programmer can also read the contents of the line control register. the read capability simplifies system programming and eliminates the need for separate storage of the line characteristics in system memory. bit 76543210 lcr dlab sbr stp eps pen stb wls wls0, wls1 these two bits specify the number of bits in each transmitted or received serial character. the encoding of bits 0 and 1 is as follows: stb this bit specifies the number of stop bits transmitted and received in each serial character. if bit 2 is a logic 0, one stop bit is generated or checked in the transmitted data. if bit 2 is a logic 1 when a 5-bit word length is selected via bits 0 and 1, one and a half stop bits are generated. if bit 2 is a logic 1 when either a 6-, 7-, or 8-bit word length is selected, two stop bits are generated. the receiver checks the first stop-bit only, regardless of the number of stop bits selected. pen this bit is the parity enable bit. when bit 3 is a logic 1, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. (the parity bit is used to produce an even or odd number of 1s when the data word bits and the parity bit are summed). eps this bit is the even parity select bit. when bit 3 is a logic 1 and bit 4 is a logic 0, an odd number of logic 1s is transmitted or checked in the data word bits and parity bit. when bit 3 is a logic 1 and bit 4 is a logic 1, an even number of logic 1s is transmitted or checked. bit 1 bit 0 character length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits peb 20560 functional block description semiconductor group 2-144 1997-11-01 2.14.1.2 programmable baud rate generator (divisors) the uart contains a programmable baud rate generator. the output frequency of the baud rate generator is 16 the baud rate [divisor = (61.44 mhz ? 5) ? (baud rate 16)]. these divisor latches must be loaded during initialization to ensure proper operation of the baud rate generator. upon loading of the divisor latche, a 16-bit baud counter is immediately loaded. table 2-35 provides decimal divisors to use with crystal frequency of 61.44 mhz. using a divisor of zero is not recommended. stp this bit is the stick parity bit. when bits 3, 4, and 5 are logic 1 the parity bit is transmitted and checked as a logic 0. if bits 3 and 5 are 1 and bit 4 is logic 0 then the parity bit is transmitted and checked as a logic 1. if bit 5 is a logic 0 stick parity is disabled. sbr this bit is the break control bit. it causes a break condition to be transmitted by the uart. when it is set to a logic 1, the serial output (sout) is forced to the spacing (logic 0) state. the break is disabled by clearing bit 6 to a logic 0. the break control bit acts only on sout and has no effect on the transmitter logic. note: this feature enables the m p to alert a terminal in a computer communications system. if the following sequence is used, no erroneous or extraneous characters will be transmitted because of the break 1. load on all os pad character in response to thre. 2. set break after the next thre. 3. wait for the transmitter to be idle, (temt = 1) and clear break when normal transmission is to be restored. during the break, the transmitter can be used as a character timer to accurately establish the break duration. dlab this bit is the divisor latch access bit. it must be set high (logic 1) to access the divisor latches of the baud generator during a read or write operation. it must be set low (logic 0) to access the receiver buffer, the transmitter holding register, or the interrupt enable register. peb 20560 functional block description semiconductor group 2-145 1997-11-01 2.14.1.3 line status register (lsr) this 8-bit register provides the m p with status information concerning the data transfer. : table 2-35 baud rates using 61.44 mhz crystal desired baud rate decimal divisor actual baud rate percentual error difference between the desired and actual baud rates 50 15360 50 0 300 2560 300 0 600 1280 600 0 1200 640 1200 0 2400 320 2400 0 4800 160 4800 0 9600 80 9600 0 19200 40 19200 0 38400 20 38400 0 76800 10 76800 0 256000 3 256000 0 bit 76543210 lsr eirf temt thre bi fe pe oe dr dr this bit is the receiver d ata r eady indicator. bit 0 is set to a logic 1 whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to a logic 0 by reading all of the data in the receiver buffer register or the flfo. peb 20560 functional block description semiconductor group 2-146 1997-11-01 oe this bit is the o verrun e rror indicator. bit 1 indicates that data in the receiver buffer register was not read by the m p before the next character was transferred into the receiver buffer register, thereby destroying the previous character. the oe indicator is set to a logic 1 upon detection of an overrun condition, and reset whenever the m p reads the contents of the line status register. if in the fifo mode data continues to fill the fifo beyond the trigger level, an overrun error will occur only after the fifo is full and the next character has been completely received in the shift register. oe is indicated to the m p as soon as it happens. the character in the shift register is overwritten, but it is not transferred to the fifo. pe this bit is the parity e rror indicator. bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even-parity-select bit. the pe bit is set to a logic 1 upon detection of a parity error and is reset to a logic 0 whenever the m p reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is revealed to the m p when its associated character is at the top of the fifo. fe this bit is the f raming e rror indicator. bit 3 indicates that the received character did not have a valid stop bit. bit 3 is set to a logic 1 whenever the stop bit following the last data bit or parity bit is detected as a logic 0 bit (spacing level). the fe indicator is reset whenever the m p reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is revealed to the m p when its associated character is at the top of the fifo. the uart will try to resynchronize after a framing error. to do this it assumes that the framing error was due to the next start bit, so it samples this start bit twice and then takes in the data. peb 20560 functional block description semiconductor group 2-147 1997-11-01 bi this bit is the b reak i nterrupt indicator. bit 4 is set to a logic 1 whenever the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). the bl indicator is reset whenever the m p reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is revealed to the m p when its associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. the next character transfer is enabled after sin goes to the marking state and receives the next valid start bit. note: bits 1 through 4 are the error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. thre this bit is the t ransmitter h olding r egister e mpty indicator. bit 5 indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the m p when the transmit holding register empty interrupt enable is set high. the thre bit is set to a logic 1 when a character is transferred from the transmitter holding register into the transmitter shift register. the bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode this bit is set when the xmit fifo is empty; it is cleared when at least 1 byte is written to the xmit fifo. temt this bit is the t ransmitter em p t y indicator. bit 6 is set to a logic 1 whenever the transmitter holding register (thr) and the transmitter shift register (tsr) are both empty. it is reset to a logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmitter fifo and shift register are both empty. eirf in the 16450 mode this is a 0. in the fifo mode eirf is set when there is at least one parity error, framing error or break indication in the fifo. eirf is cleared when the m p reads the lsr, if there are no subsequent errors in the fifo. note: the line status register is intended for read operations only. writing to this register is not recommended as this operation is only used for factory testing. peb 20560 functional block description semiconductor group 2-148 1997-11-01 2.14.1.4 fifo control register (fcr) this is a write only register at the same address location as the iir (the iir is a read only register). this register is used to enable the flfos, clear the flfos, set the rcvr fifo trigger level, and select the type of dma signaling. bit 76543210 fcr fcr7 fcr6 dms tfr rfr fewo fewo writing a 1 to fewo enables both the xmit and rcvr flfos. resetting fewo will clear all bytes in both flfos. when changing from fifo mode to 16450 mode and vice versa, data is automatically cleared from the flfos. this bit must be a 1 when other fcr bits are written to, or they will not be programmed. rfr writing a 1 to rfr clears all bytes in the rcvr fifo and resets its counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self-clearing. tfr writing a 1 to tfr clears all bytes in the xmit fifo and resets its counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self-clearing. dms setting dms to a 1 will cause the rxrdy and txrd pins to change from mode 0 to mode 1 if fewo = 1 (see description of rxrdy and txrdy pins). bit 4 and 5 these bits are reserved for future use. fcr7:6 fcr6 and fcr7 are used to set the trigger level for the rcvr fifo interrupt. bit 7 bit 6 rcvr fifo trigger level (bytes) 0001 0104 1008 1114 peb 20560 functional block description semiconductor group 2-149 1997-11-01 2.14.1.5 interrupt identification register (iir) in order to provide minimum software overhead during data character transfers, the uart prioritizes interrupts into four levels and records these in the interrupt identification register. the four levels of interrupt conditions in order of priority are receiver line status, received data ready, transmitter holding register empty, and modem status. when the m p accesses the iir, the uart freezes all interrupts and indicates the highest priority pending interrupt to the cpu. while this m p access is occurring, the uart records new interrupts, but does not change its current indication until the access is complete. table 2-31 shows the contents of the iir. details on each bit follow: bit 76543210 iir fe 0 0 iidb2 iidb1 iidb0 table 2-36 iir register fifo mode only interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control 0 001C none none C 0 1 1 0 highest receiver line status overrun error or parity error or framing error or break interrupt reading the line status register 0 1 0 0 second receiver data available receiver data available or trigger level reached reading the receiver buffer register or the fifo drops below the trigger level peb 20560 functional block description semiconductor group 2-150 1997-11-01 1 1 0 0 second character time-out indication no characters have been removed from or input to the rcvr fifo during the last 4 char. times and there is at least 1 char. in it during this time reading the receiver buffer register 0 0 1 0 third transmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing into the transmitter holding register 0 0 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register table 2-36 iir register (contd) fifo mode only interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control peb 20560 functional block description semiconductor group 2-151 1997-11-01 2.14.1.6 interrupt enable register (ier) this register enables the five types of uart interrupts. each interrupt can individually activate the interrupt (intr) output signal. it is possible to totally disable the interrupt system by resetting bits 0 through 3 of the interrupt enable register (ier). similarly, setting bits of this register to a logic 1 enables the selected interrupt(s). disabling an interrupt prevents it from being indicated as active in the iir and from activating the intr output signal. all other system functions operate in their normal manner, including the setting of the line status and modem status registers. 2.14.1.7 modem control register (mcr) this register controls the interface with the modem or data set (or a peripheral device emulating a modem). the contents of the modem control register (mcr) are indicated in table 2-31 . bit 0 this bit can be used in an interrupt environment to indicate whether an interrupt condition is pending. when bit 0 is a logic 0, an interrupt is pending and the iir contents may be used as a pointer to the appropriate interrupt service routine. when bit 0 is a logic 1, no interrupt is pending. iidb0; iidb1 these two bits of the iir are used to identify the highest priority interrupt pending as indicated in table 2-36 . iidb2 in the 16c450 mode this bit is 0. in the fifo mode this bit is set along with bit 2 when a time-out interrupt is pending. bits 4 and 5 these two bits of the iir are always logic 0. fe these two bits are set when fewo = 1. bit 76543210 ier 0000 edssi erlsi etbei erbfi erbfi this bit enables the received data available interrupt (and time-out interrupts in the fifo mode) when set to logic 1. etbei this bit enables the transmitter holding register empty interrupt when set to logic 1. erlsi) this bit enables the receiver status interrupt when set to logic 1. edssi this bit enables the modem status interrupt when set to logic 1. bit 4 through 7 these four bits are always logic 0. peb 20560 functional block description semiconductor group 2-152 1997-11-01 details on each bit follow: bit 76543210 mcr 0 0 0 loop0 out2 out1 rts dtr dtr this bit controls the data terminal ready output. when bit 0 is set to a logic 1, the dtr output is forced to a logic 0. when bit 0 is reset to a logic 0, the dtr output is forced to a logic 1. note: the dtr output of the uart may be applied to an eia inverting line driver (such as the 1488) to obtain the proper polarity input at the succeeding modem or data set. rts this bit controls the request to send output. bit 1 affects the rts output in a manner identical to that described above for bit 0. out1 this bit controls the output 1 signal, which is an auxiliary user- designated output. bit 2 affects the out1 output in a manner identical to that described above for bit 0. out2 this bit controls the output 2 signal, which is an auxiliary user-designated output. bit 3 affects the out2 output in a manner identical to that described above for bit 0. loop this bit provides a local loopback feature for diagnostic testing of the uart. when bit 4 is set to logic 1, the following occurs: the transmitter serial output (sout) is set to the marking (logic 1) state; the receiver serial input (sin) is disconnected; the output of the transmitter shift register is looped back into the receiver shift register input; the four modem control inputs (cts , dsr , rl , and dcd ) are disconnected; and the four modem control outputs (dtr , rts , out1 , and out2 ) are internally connected to the four modem control inputs. the modem control output pins are forced to their inactive state (high). in the diagnostic mode, data that is transmitted is immediately received. this feature allows the processor to verify the transmit and received data paths of the uart. in the diagnostic mode, the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational, but the interrupts sources are now the lower four bits of the modem control register instead of the four modem control inputs. the interrupts are still controlled by the interrupt enable register. bits 5 through 7 these bits are permanently set to logic 0. peb 20560 functional block description semiconductor group 2-153 1997-11-01 2.14.1.8 modem status register (msr) this register provides the current state of the control lines from the modem (or peripheral device) to the cpu. in addition to this current-state information, four bits of the modem status register provide change information. these bits are set to a logic 1 whenever a control input from the modem changes state. they are reset to logic 0 whenever the m p reads the modem status register. table 2-31 shows the contents of the msr. details on each bit follow. bit 76543210 msr dcd rl dsr cts ddcd teri ddsr dcts dcts this bit is the delta clear to send indicator. bit 0 indicates that the cts input to the chip has changed state since the last time it was read by the cpu. ddsr this bit is the delta data set ready indicator. bit 1 indicates that the dsr input to the chip has changed state since the last time it was read by the cpu. teri this bit is the trailing edge of ring indicator detector. bit 2 indicates that the rl input to the chip has changed from a low to a high state. ddcd this bit is the delta data carrier detect indicator. bit 3 indicates that the dcd input to the chip has changed state: note: whenever bit 0, 1, 2, or 3 is set to logic 1, a modem status interrupt is generated. cts this bit is the complement of the clear to send input. if bit 4 (loop) of the mcr is set to a 1, this bit is equivalent to rts in the mcr. dsr this bit is the complement of the data set ready input. if bit 4 of the mcr is set to a 1, this bit is equivalent to dtr in the mcr. ri this bit is the complement of the ring indicator input. if bit 4 of the mcr is set to a 1, this bit is equivalent to out1 in the mcr. dcd this bit is the complement of the data carrier detect input. if bit 4 of the mcr is set to a 1, this bit is equivalent to out2 in the mcr. peb 20560 functional block description semiconductor group 2-154 1997-11-01 2.14.1.9 scratchpad register (scr) this 8-bit read/write register does not control the uart in any way. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. 2.14.2 fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (fewo = 1, erbfi = 1) rcvr interrupts will occur as follows: a) the receive data available interrupt will be issued to the m p when the fifo has reached its programmed trigger level; it will be cleared as soon as the fifo drops below its programmed trigger level. b) the iir receive data available indication also occurs when the fifo trigger level is reached, and like the interrupt it is cleared when the fifo drops below the trigger level. c) the receiver line status interrupt (iir = 06), as before, has higher priority than the received data available (iir = 04) interrupt. d) the data ready bit (dr) is set as soon as a character is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, rcvr fifo time-out interrupts will occur as follows: a) a fifo time-out interrupt will occur, if the following conditions exist: C at least one character is in the fifo C the most recent serial character received was longer than 4 continuous character times ago (if 2 stop bits are programmed the second one is included in this time delay). C the most recent m p read of the fifo was longer than 4 continuous character times ago. this will cause a maximum character received to interrupt issued delay of 160 ms at 300 baud with a 12-bit character. b) character times are calculated by using the rclk input for a clock signal (this makes the delay proportional to the baudrate). c) when a time-out interrupt has occurred it is cleared and the timer reset when the m p reads one character from the rcvr fifo. d) when a time-out interrupt has not occurred the time-out timer is reset after a new character is received or after the m p reads the rcvr fifo. bit 7 0 scr xxxxxxxx peb 20560 functional block description semiconductor group 2-155 1997-11-01 when the xmit fifo and transmitter interrupts are enabled (fewo = 1, etbei = 1), xmit interrupts will occur as follows: a) the transmitter holding register interrupt (02) occurs when the xmit fifo is empty; it is cleared as soon as the transmitter holding register is written to (1 to 16 characters may be written to the xmit fifo while servicing this interrupt) or the iir is read. b) the transmitter fifo empty indication will be delayed 1 character time minus the last stop bit time whenever the following occurs: thre = 1, and there have not been at least two bytes at the same time in the transmit fifo since the last thre = 1. the first transmitter interrupt after changing fewo will be immediate, if it is enabled. character time-out and rcvr fifo trigger level interrupts have the same priority as the current received data available interrupt; xmit fifo empty has the same priority as the current transmitter holding register empty interrupt. 2.14.3 fifo polled mode operation with fewo = 1 resetting erbfi, etbei, erlsi, edssi or all to zero puts the uart in the fifo polled mode of operation. since the rcvr and xmitter are controlled separately either one or both can be in the polled mode of operation. in this mode the users program will check rcvr and xmitter status via the lsr. as stated previously: C dr will be set as long as there is one byte in the rcvr fifo. C lsr1 to lsr4 will specify which error(s) has occurred. character error status is handled the same way as when in the interrupt mode, the iir is not affected since erlsi = 0. C thre will indicate when the xmit fifo is empty. C temt will indicate that both the xmit fifo and shift register are empty. C eirf will indicate whether there are any errors in the rcvr fifo. there is no trigger level reached or time-out condition indicated in the fifo polled mode, however, the rcvr and xmit flfos are still fully capable of holding characters. peb 20560 functional block description semiconductor group 2-156 1997-11-01 2.15 general purpose i/o port (gpio) the general purpose i/o port (gpio) is multifunctional system. gpio has three working modes. gpio can provide the i/o port unit, the sacco-b0 unit or the uart unit. gpio has four ports. each port has special purpose 2.15.1 i/o port support lines (mode 0) in i/o port mode each port can be configure as input port or as output port. when the data changes on input port, the doc sends an interrupt. the version 2.1 provides a mask register vintmask thus changes of the port values do not lead to cpu interrupt generation. interrupt mask register for gpio (vintmask) address 328a h read / write reset value 00 h note: bits 74 are not used, and are read as 0. the gpio interrupt is reset when the vdatr register is read. mp30 mask i/o port 3 to 0 bits 0 = the interrupt is enabled (the interrupt is not masked) 1 = the interrupt is disabled (the interrupt is masked) 2.15.2 sacco-b0 support lines (mode 1) when gpio is configured to sacco-b0 mode: ? sacco-b0 drives drqtb0 signal (dma transmit request) trough port0. ? sacco-b0 drives drqrb0 (dma receive request) signal trough port1. ? sacco-b0 gets dackb0 (dma acknowledge) signal trough port2. ? sacco-b0 gets hfscb0 (external frame synchronization clock) signal trough port3. 2.15.3 uart support lines (mode 2) when gpio configure to uart mode: ? uart gets dsr (data set ready) signal trough port0. ? uart drives dtr (data transmit ready) signal trough port1. ? uart gets ri (ring indicator) signal trough port2. ? uart gets dcd (data carrier detect) signal trough port3. bit 7 43210 vintmask 0000mp3mp2mp1mp0 peb 20560 functional block description semiconductor group 2-157 1997-11-01 2.15.4 configuration register (vcfgr) address: 320 h m p access mode: read/write reset value: 00 h mode20 gpio mode. 100io mode 010sacco-b0 001 - uart all other values are not defined. after reset gpio is configured to io mode, eventhough vcfgr reset mode is 00h. dir 30 this field is valid only when in io mode. each bit in the field defines if the respective port direction is input or output. 0 - input direction. 1 - output direction. 2.15.5 data register (vdatr) address: 321 h m p access mode: read/write reset value: 00 h dat 30 data which is written to this field drives the ports, when gpio is configured to io mode and the ports are configured as outputs. each bit in the field drives the respective port, when its configured as output. when a port is configured as input, the respective datn-field bit is not used. when the gpio is not configured to io mode vdatr is not used. during read instruction of vdatr the value read, is the value which is driven on the ports, independently of the gpio mode, and the configured direction of each port. each unused bit will be read as 0. bit 7 bit 0 unused mode2 mode1 mode0 dir3 dir2 dir1 dir0 bit 7 bit 0 unused unused unused unused dat3 dat2 dat1 dat0 peb 20560 functional block description semiconductor group 2-158 1997-11-01 2.15.6 version number register (vnr) address: 322 h m p access mode: read reset value: 00 h vnr30 doc version number. v1.1 0000 v2.1 0001 each unused bit will be read as 0. 2.16 boundary scan support (jtag) the doc provides a complete boundary scan support according to ieee std. 1149.1 specification for a cost effective board testing. it consists of: ? test access port controller (tap) ? four dedicated pins: jtclk, tms, tdi, tdo ? tri-state of doc output lines for board tests in production ? 32-bit doc id register all doc-pins except the power supply pins ( v dd , v ddp ), the ground pins ( v ss ) and the external quartz clock pins (clk40-xi, clk40-xo), are included in the boundary scan. depending on the pin functionality, one, two or three boundary scan cells are provided. a bsdl (boundary scan description language) file for the doc is available. 2.16.1 boundary scan when the tap-controller is in the appropriate mode data is shifted into/out of the boundary scan via the pins tdi/tdo using the 6.25-mhz clock on pin tck. the elic-pins are included in the following sequence in the boundary scan. bit 7 bit 0 unused unused unused unused vnr3 vnr2 vnr1 vnr0 table 2-37 boundary scan cell types pin type number of boundary scan cells usage input 1 input output 2 output, enable i/o 3 input, output, enable peb 20560 functional block description semiconductor group 2-159 1997-11-01 2.16.2 tap-controller the tap contoller implements a state machine defined in the jtag standard ieee1149.1. the instruction register of the controller is extended to 4 bits in order to increase the number of instructions. this is necessary for the use of the serial emulation via the boundary scan interface: the extended tap controller uses a modified data path: the next paragraph specifies the functionality of each instruction: ? idcode , the 32-bit identification register is serially read out via tdo. it contains the version number (4 bit), the device code (16 bit) and the manufacturer code (11 bits). the lsb is fixed to 1. table 2-38 instruction code of 4 bit tap controller instruction code extest 0000 intest 0001 sample / preload 0010 idcode 0011 serial emulation 01xx unused 10xx bypass 11xx table 2-39 data path of 4 bit tap controller instruction code input data path output 11xx tdi ? tdo 000x, 0010 bsout ? tdo 0011 bsout_id ? tdo 01xx tdi2: seib:tdo (internal) ? tdo 10xx tdi3: v ss (not used, internal) ? tdo ver. no. device code (part number) manufacturer code (id) tdi ? 0001 0000 0000 0011 1000 0000 1000 001 1 ? tdo 0000 = doc v1.1 0001 = doc v2.1 peb 20560 functional block description semiconductor group 2-160 1997-11-01 siemens provides for the doc upon request a boundary scan description language, so called dsdl file. 2.17 reset logic during doc hw reset: ? all signal lines with input/output (i/o) capability are switched to input direction. ? the state of each output pin is as defined in the pin description tables ( table 1-1 to table 1-7 ). ? the integrated clock generator provides the necessary clocks to both elics. both elics pdc and dcl are driven by the internal pdc8 (= clk16 div. by 2). both elics pfs and fsc are driven by the internal pfs (= clk16 div. by 2048). ? pdc2, pdc4, pdc8, pfs, dcl and fsc are driven internally, but these i/o pins are not driven by the doc, and stay in tri-state. pdc2, pdc4, pdc8 and pfs starts to be driven by the doc after the first write access to ccsel0, and only if the doc were configured as master. dcl and fsc starts to be driven by the doc after the first write access to ccsel1, and only if these signals were configured as outputs. ? the oak clock frequency is defined according to frq10 input pins. if frq10 pins are 10 (oak clock frequency = 40 mhz), then a 40 mhz crystal must be connected to pins clk40-xi and clk40-xo. ? clk 61.44 mhz must be provided to the doc via clk61 input pin. ? clk30, clk15 and clk7 are driven by the doc, as usual ? all the registers get the reset value, that defined in the register overview, section 5 . peb 20560 operational description semiconductor group 3-1 1997-11-01 3 operational description 3.1 elic0 and elic1 the elic, designed as a flexible line-card controller, has the following main applications: C digital line cards, with the cfi typically configured as iom-2, iom-1 (mux) or sld. C analog line cards, with the cfi typically configured as iom-2 or sld. C key systems, where the elics ability to mix cfi-configurations is utilized. to operate the elic the user must be familiar with the devices microprocessor interface, interrupt structure and reset logic. also, the operation of the elics component parts should be understood. the devices major components are the epic-1, the sacco-a and sacco-b, and the d-channel arbiter. while epic-1 and sacco-b may all be operated independently of each other, the d-channel arbiter can be used to interface the sacco-a to the cfi of the epic-1. this mode of operation may be considered to utilize the elic most extensively. the initialization example, with which this operational description closes, will therefore set the elic to operate in this manner. 3.1.1 interrupt structure and logic the elic-signals events that the m p should know about immediately by emitting an interrupt request on the int -line. to indicate the detailed cause of the request a tree of interrupt status registers is provided. figure 3-1 elic ? interrupt structure itd05843 exb iep ida iwd icb exa ica ista_a mask_a exir_a ista_b mask_b exir_b mask_e ista_e watchdog timer d-channel arbiter epic hdlc channel b, extended hdlc channel b hdlc channel a, extended hdlc channel a ista mask r peb 20560 operational description semiconductor group 3-2 1997-11-01 when serving an elic-interrupt, the user first reads the top level interrupt status register (ista). this register flags which subblock has generated the request. if a subblock can issue different interrupt types a local ista/exir exists. a read of the top level ista-register resets bits iwd and ida. the other bits are reset when reading the corresponding local ista- or exir-registers. the int -output is level active. it stays active until all interrupt sources have been serviced. if a new status bit is set while an interrupt is being serviced, the int stays active. however, for the duration of a write access to the mask-register the int -line is deactivated. when using an edge-triggered interrupt controller, it is thus recommended to rewrite the mask-register at the end of any interrupt service routine. masking interrupts the watchdog timer interrupt can not be masked. setting the mask.ida-bit masks the ista.ida-interrupt: a d-channel arbiter interrupt will then neither activate the int -line nor be indicated in the ista-register. setting the mask.iep/exb/icb/exa or ica-bits only masks the int -line; that is, with a set top level mask bit these epic-1 and sacco interrupts are indicated in the ista-register but they will not activate the int -line. for the ista_e, ista_a and ista_b registers local masking is also provided. every interrupt source indicated in these registers can be selectively masked by setting the respective bit of the local mask-register. such locally masked interrupts will not be indicated in the local or the top ista-register, nor will they activate the int -line. locally masked interrupts are internally stored. thus, resetting the local mask will release the interrupt to be indicated in the local interrupt register, flagged in the top level ista-register, and to activate the int -line. 3.1.2 clocking to operate properly, the elic always requires a pdc-clock. to synchronize the pcm-side, the elic should normally also be provided with a pfs-strobe. in most applications, the dcl and fsc will be output signals of the elic, derived from the pdc via prescalers. if the required cfi-data rate cannot be derived from the pdc, dcl and fsc can also be programmed as input signals. this is achieved by setting the epic-1 cmd1:css-bit. frequency and phase of dcl and fsc may then be chosen almost independently of the frequency and phase of pdc and pfs. however, the cfi-clock source must still be synchronous to the pcm-interface clock source; i.e. the clock source for the cfi-interface and the clock source for the pcm-interface must be derived from the same master clock. peb 20560 operational description semiconductor group 3-3 1997-11-01 3.1.3 epic ? -1 operation the epic-1 component of the elic is principally an intelligent switch of pcm-data between two serial interfaces, the system interface (pcm-interface) and the configurable interface (cfi). up to 128 channels per direction can be switched dynamically between the cfi and the pcm-interfaces. the epic-1 performs non-blocking space and time switching for these channels which may have a bandwidth of 16, 32 or 64 kbit/s. both interfaces can be programmed to operate at different data rates of up to 8.192 mbit/s. the pcm-interface consists of up to four duplex ports with a tri-state control signal for each output line. the configurable interface can be selected to provide either four duplex ports or 8 bi-directional (i/o) ports. the configurable interface incorporates a control block (layer-1 buffer) which allows the m p to gain access to the control channels of an iom- (isdn-oriented modular) or sld- (subscriber line data) interface. the epic-1 can handle the layer-1 functions buffering the c/i and monitor channels for iom compatible devices and the feature control and signaling channels for sld compatible devices. one major application of the epic-1 is therefore as line card controller on digital and analog line cards. the layer-1 and codec devices are connected to the cfi, which is then configured to operate as, iom-2, sld or multiplexed iom-1 interface. the configurable interface of the epic-1 can also be configured as plain pcm-interface i.e. without iom- or sld-frame structure. since its possible to operate the two serial interfaces at different data rates, the epic-1 can then be used to adapt two different pcm- systems. the epic-1 can handle up to 32 isdn-subscribers with their 2b + d channel structure or up to 64 analog subscribers with their 1b channel structure in iom-configuration. in sld- configuration up to 16 analog subscribers can be accommodated. the system interface is used for the connection to a pcm-back plane. on a typical digital line card, the epic-1 switches the isdn b-channels and, if required, also the d-channels to the pcm-back plane. due to its capability to dynamically switch the 16-kbit/s d-channel, the epic-1 is one of the fundamental building blocks for networks with either central, decentral or mixed signaling and packet data handling architecture. 3.1.3.1 pcm-interface the serial pcm-interface provides up to four duplex ports consisting each of a data transmit (txd#), a data receive (rxd#) and a tri-state control (tsc# ) line. the transmit direction is also referred to as the upstream direction, whereas the receive direction is referred to as the downstream direction. data is transmitted and received at normal ttl / cmos-levels, the output drivers being of the tri-state type. unassigned time-slots may be either be tri-stated, or programmed to transmit a defined idle value. the selection of the states high impedance and idle value can be performed with a two bit resolution. this tri-state capability allows several peb 20560 operational description semiconductor group 3-4 1997-11-01 devices to be connected together for concentrator functions. if the output driver capability of the epic-1 should prove to be insufficient for a specific application, an external driver controlled by the tsc# can be connected. the pcm-standby function makes it possible to switch all pcm-output lines to high impedance with a single command. internally, the device still works normally. only the output drivers are switched off. the number of time-slots per 8-khz frame is programmable in a wide range (from 4 to 128). in other words, the pcm-data rate can range between 256 kbit/s up to 8.192 mbit/s . since the overall switching capacity is limited to 128 time-slots per direction, the number of pcm-ports also depends on the required number of time-slots: in case of 32 time-slots per frame (2.048 mbit/s) for example, four highways are available, in case of 128 time-slots per frame (8.192 mbit/s), only one highway is available. the partitioning between number of ports and number of bits per frame is defined by the pcm-mode . there are four pcm-modes. the timing characteristics at the pcm-interface (data rate, bit shift, etc.) can be varied in a wide range, but they are the same for each of the four pcm-ports, i.e. if a data rate of 2.048 mbit/s is selected, all four ports run at this data rate of 2.048 mbit/s. the pcm-interface has to be clocked with a pcm-data clock (pdc) signal having a frequency equal to or twice the selected pcm-data rate. in single clock rate operation, a frame consisting of 32 time-slots, for example, requires a pdc of 2.048 mhz. in double clock rate operation, however, the same frame structure would require a pdc of 4.096 mhz. for the synchronization of the time-slot structure to an external pcm-system, a pcm- framing signal (pfs) must be applied. the epic-1 evaluates the rising pfs edge to reset the internal time-slot counters. in order to adapt the pfs-timing to different timing requirements, the epic-1 can latch the pfs-signal with either the rising or the falling pdc- edge. the pfs-signal defines the position of the first bit of the internal pcm-frame. the actual position of the external upstream and downstream pcm-frames with respect to the framing signal pfs can still be adjusted using the pcm-offset function of the epic-1. the offset can then be programmed such that pfs marks any bit number of the external frame. furthermore it is possible to select either the rising or falling pdc-clock edge for transmitting and sampling the pcm-data. usually, the repetition rate of the applied framing pulse pfs is identical to the frame period (125 m s). if this is the case, the loss of synchronism indication function can be used to supervise the clock and framing signals for missing or additional clock cycles. the epic-1 checks the pfs-period internally against the duration expected from the programmed data rate. if, for example, double clock operation with 32 time-slots per frame is programmed, the epic-1 expects 512 clock periods within one pfs-period. the synchronous state is reached after the epic-1 has detected two consecutive correct peb 20560 operational description semiconductor group 3-5 1997-11-01 frames. the synchronous state is lost if one bad clock cycle is found. the synchronization status (gained or lost) can be read from an internal register and each status change generates an interrupt. 3.1.3.2 configurable interface the epic-1 provides up to four ports consisting each of a data output (dd#) and a data input (du#) line. the output pins are called data downstream pins and the input pins are called data upstream pins. these modes are especially suited to realize a standard serial pcm-interface (pcm-highway) or to implement an iom (isdn-oriented modular) interface. the iom-interface generated by the epic-1 offers all the functionality like c/i- and monitor channel handling required for operating all kinds of iom compatible layer-1 and codec devices. data is transmitted and received at normal ttl/cmos-levels at the cfi. tri-state or open-drain output drivers can be selected. in case of open-drain drivers, external pull-up resistors are required. unassigned output time-slots may be switched to high impedance or be programmed to transmit a defined idle value. the selection between the states high impedance or idle value can be performed on a per time-slot basis. the cfi-standby function switches all cfi-output lines to high impedance with a single command. internally the device still works normally, only the output drivers are switched off. the number of time-slots per 8-khz frame is programmable from 2 to 128. in other words, the cfi-data rate can range between 128 kbit/s up to 8.192 mbit/s . since the overall switching capacity is limited to 128 time-slots per direction, the number of cfi- ports also depends on the required number of time-slots: in case of 32 time-slots per frame (2.048 mbit/s) for example, four highways are available, in case of 128 time-slots per frame (8.192 mbit/s), only one highway is available. usually, the number of bits per 8-khz frame is an integer multiple of the number of time-slots per frame (1 time-slot = 8 bits). the timing characteristics at the cfi (data rate, bit shift, etc.) can be varied in a wide range, but they are the same for each of the four cfi-ports, i.e. if a data rate of 2.048 mbit/s is selected, all four ports run at this data rate of 2.048 mbit/s. it is thus not possible to have one port used in iom-2 line card mode (2.048 mbit/s) while another port is used in iom-2 terminal mode (768 kbit/s)! note: the integrated pcm-dsp interface unit (pediv) works correctly only at 2.048 mbit/s or 4.096 mbit/s data rate. the clock and framing signals necessary to operate the configurable interface may be derived either from the clock and framing signals of the pcm-interface (pdc and pfs pins), or may be fed in directly via the dcl- and fsc-pins. in the first case, the cfi-data rate is obtained by internally dividing down the pcm-clock signal pdc. several prescaler factors are available to obtain the most commonly used peb 20560 operational description semiconductor group 3-6 1997-11-01 data rates. a cfi reference clock (crcl) is generated out of the pdc-clock. the pcm-framing signal pfs is used to synchronize the cfi-frame structure. additionally, the epic-1 generates clock and framing signals as outputs to operate the connected subscriber circuits such as layer-1 and codec filter devices. the generated data clock dcl has a frequency equal to or twice the cfi-data rate. note that if pfs is selected as the framing signal source, the fsc-signal is an output with a fixed timing relationship with respect to the cfi-data lines. the relationship between fsc and the cfi-frame depends only on the selected fsc-output wave form (cmd2- register). the cfi-offset function shifts both the frame and the fsc-output signal with respect to the pfs-signal. in the second case, the cfi-data rate is derived from the dcl-clock, which is now used as an input signal. the dcl-clock may also first be divided down by internal prescalers before it serves as the cfi reference clock crcl and before defining the cfi-data rate. the framing signal fsc is used to synchronize the cfi-frame structure. 3.1.3.3 switching functions the major tasks of the epic-1 part is to dynamically switch pcm-data between the serial pcm-interface, the serial configurable interface (cfi) and the parallel m p-interface. all possible switching paths are shown in figure 3-2 . figure 3-2 switching paths inside the epic ? -1 note that the time-slot selections in upstream direction are completely independent of the time-slot selections in downstream direction. its05844 p p interface epic r 1 2 3 4 5 6 c f i p c m peb 20560 operational description semiconductor group 3-7 1997-11-01 cfi - pcm time-slot assignment switching paths 1 and 2 of figure 3-2 can be realized for a total number of 128 channels per path, i.e. 128 time-slots in upstream and 128 time-slots in downstream direction. to establish a connection, the m p writes the addresses of the involved cfi and pcm time-slots to the control memory. the actual transfer is then carried out frame by frame without further m p-intervention. the switching paths 5 and 6 can be realized by programming time-slot assignments in the control memory. the total number for such loops is limited to the number of available time-slots at the respective opposite interface, i.e. looping back a time-slot from cfi to cfi requires a spare upstream pcm time-slot and looping back a time-slot from pcm to pcm requires a spare downstream and upstream cfi time-slot. time-slot switching is always carried out on 8-bit time-slots, the actual position and number of transferred bits can however be limited to 4-bit or 2-bit sub time-slots within these 8-bit time-slots. on the cfi-side, only one sub time-slot per 8-bit time-slot can be switched, whereas on the pcm-interface up to 4 independent sub time-slots can be switched. sub time-slot switching sub time-slot positions at the pcm-interface can be selected at random, i.e. each single pcm time-slot-may contain any mixture of 2- and 4-bit sub time-slots. a pcm time-slot may also contain more than one sub time-slot. on the cfi however, two restrictions must be observed: C each cfi time-slot may contain one and one only sub time-slot. C the sub-slot position for a given bandwidth within the time-slot is fixed on a per port basis. m p-transfer switching paths 3 and 4 of figure 3-2 can be realized for all available time-slots. path 3 can be implemented by defining the corresponding cfi time-slots as m p-channels or as pre-processed channels. each single time-slot can individually be declared as m p-channel . if this is the case, the m p can write a static 8-bit value to a downstream time-slot which is then transmitted repeatedly in each frame until a new value is loaded. in upstream direction, the m p can read the received 8-bit value whenever required, no interrupts being generated. the pre-processed channel option must always be applied to two consecutive time-slots. the first of these time-slots must have an even time-slot number. if two time- slots are declared as pre-processed channels, the first one can be accessed by the monitor/feature control handler, which gives access to the frame via a 16-byte fifo. although this function is mainly intended for iom- or sld-applications, it could also be used to transmit or receive a burst of data to or from a 64-kbit/s channel. the second peb 20560 operational description semiconductor group 3-8 1997-11-01 pre-processed time-slot, the odd one, is also accessed by the m p. in downstream direction a 4-, 6- or 8-bit static value can be transmitted. in upstream direction the received 8-bit value can be read. additionally, a change detection mechanism will generate an interrupt upon a change in any of the selected 4, 6 or 8 bits. pre-processed channels are usually programmed after control memory (cm) reset during device initialization. resetting the cm sets all cfi time-slots to unassigned channels (cm code 0000). of course, pre-processed channels can also be initialized or re-initialized in the operational phase of the device. to program a pair of pre-processed channels the correct code for the selected handling scheme must be written to the cm. figure 3-3 gives an overview of the available pre-processing codes and their application. note: to operate the d-channel arbiter, an iom-2 configuration with central-, or decentral d-channel handling should be programmed. with the d-channel arbiter enabled, d-channel bits are handled by the sacco-a. peb 20560 operational description semiconductor group 3-9 1997-11-01 figure 3-3 pre-processed channel codes itd05846 signaling channel feature control channel sig m m m m m m m m control channel monitor channel m m sig m m m m m m m m d d mmmmmm mm c/i mm monitor channel control channel control channel monitor channel m m c/i m m m m m m m m 1 1 0 1 0 1 0 1 xx xx x 0000 xx x c/i 1 1 1 0 0 0 1 1 1 1 000 11 1 c/i x x 0 1 0 1 1 0 11 odd time-slot even time-slot upstream preprocessed channels input from the configurable interface odd control memory address maar = 1......1 code field macr = 011... data field madr = ...... madr = ...... data field macr = 0111... code field maar = 1......1 even control memory address (e.g. sld) signaling 8 bit 6 bit iom ) r (e.g. analog signaling handling d channel central handling d channel decentral sig actual value sig stable value xx -- : monitor channel bits, these bits are treated by the monitor/feature control handler m - : inactive sub. time-slot, in downstream direction these bits are tristated (omdr : cos = 0) or set to logical 1 (omdr :cos = 1) c/i : command/indication channel, these bits are exchanged between the cfi in/output and the cm data field. a change of the c/i bits in upstream direction causes an interrupt (ista : sfi). the address of the change is stored in the cififo d : d channel, these d channel bit switched to and from the pcm interface, or handled by the sacco_a, it the d channel arbiter is enabled. sig : signaling channel, these bits are exchanged between the cfi in/output and tne cm data field. the sig value which was present in the last frame is stored as the actual value in the even address cm location. the stable value is updated if a valid change in the actual value has been detected according to the last look algorithm. a change of the sig stable value in upstream direction causes an interrupt (ista : cfi). the address of the change is stored in the cififo. actual value stable value time-slot a 2 bit sub. pcm code for pointer to a pcm time-slot du application sig actual value sig stable value itd05845 decentral d channel handling central d channel handling signaling (e.g. analog r iom ) 6 bit 8 bit signaling (e.g. sld) sacco_a d channel handling dd application even control memory address maar = 0......0 code field macr = 0111... data field madr = ...... madr = ...... data field macr = 0111... code field maar = 0......1 odd control memory address output at the configurable interface downstream preprocessed channels even time-slot odd time-slot 1 0 1 0 11 1 c/i m r when using handshaking, set mr = 1 sig 0 1 0 1 1 0 1 0 sig 11 c/i 1 1 1 0 1 0 1 1 1 1 000 11 1 c/i x x x 1 1 0 1 x x xx x xx xx x 1 0 11 xx x xx xx x 1 0 11 xx x xx xx x 1 0 11 xx x pointer to a pcm time-slot pcm code for a 2 bit sub. time-slot mmmmmm mm c/i mm monitor channel control channel control channel monitor channel m m c/i m m m m m m m m dd mmmmmm mm sig mm monitor channel control channel mmmmmm mm sig feature control channel signaling channel d d mmmmmm mm c/i mm monitor channel control channel -- peb 20560 operational description semiconductor group 3-10 1997-11-01 synchronous transfer for two channels, all switching paths of figure 3-2 can also be realized using synchronous transfer. the working principle is that the m p specifies an input time-slot (source) and an output time-slot (destination). both source and destination time-slots can be selected independently from each other at either the pcm- or cfi-interfaces. in each frame, the epic-1 first transfers the serial data from the source time-slot to an internal data register from where it can be read and if required overwritten or modified by the m p. this data is then fed forward to the destination time-slot. 3.1.3.4 special functions hardware timer the epic-1 provides a hardware timer which continuously interrupts the m p after programmable time periods. the timer period can be selected in the range of 250 m s up to 32 ms in multiples of 250 m s. beside the interrupt generation, the timer can also be used to determine the last look period for 6 and 8-bit signaling channels on iom-2 and sld-interfaces and for the generation of an fsc-multiframe signal. power and clock supply supervision the + 3.3 v power supply line and the clock lines are continuously checked by the epic-1 for spikes that may disturb its proper operation. if such an inappropriate clocking or power failure occurs, the m p is requested to reinitialize the device. 3.1.4 sacco - a/b chapter 2.1.2.5 provides a detailed functional sacco-description. this operational section will therefore concentrate on outlining how to run these hdlc-controllers. with the sacco initialized as outlined in chapter 3.1.6.3 , it is ready to transmit and receive data. data transfer is mainly controlled by commands from the cpu to the sacco via the cmdr-register, and by interrupt indications from sacco to cpu. additional status information, which need not trigger an interrupt, is available in the star-register. 3.1.4.1 data transmission in interrupt mode in transmit direction 2 32-byte fifo-buffers (transmit pools) are provided for each channel. after checking the xfifo-status by polling the transmit fifo write enable bit (xfw in star-register) or after a transmit pool ready (xpr) interrupt, up to 32 bytes may be entered by the cpu to the xfifo. the transmission of a frame can then be started issuing a xtf/xpd or xdd command via the cmdr-register. if prepared data is sent, an end of message indication (cmdr:xme) must also be set. if transparent or direct data is sent, cmdr:xme may but peb 20560 operational description semiconductor group 3-11 1997-11-01 need not be set. if cmdr:xme is not set, the sacco will repeatedly request for the next data block by means of a xpr-interrupt as soon as the cpu accessible part of the xfifo is available. this process will be repeated until the cpu indicates the end of message per command, after which frame transmission is ended by appending the crc and closing flag sequence. if no more data is available in the xfifo prior to the arrival of xme, the transmission of the frame is terminated with an abort sequence and the cpu is notified per interrupt (exir:xdu). the frame may also be aborted per software (cmdr:xres). figure 3-4 outlines the data transmission sequence from the cpus point of view: figure 3-4 interrupt driven transmission sequence (flow diagram) itd05847 xpr interrupt or set xfw bit in star register n command write data (up to 32 bytes) to xfifo end of massage ? command xme+ xtf/xpd or xdd end transmit pool ready ? start n y y xtf or xdd peb 20560 operational description semiconductor group 3-12 1997-11-01 ) figure 3-5 interrupt driven transmission sequence example 3.1.4.2 data transmission in dma-mode prior to data transmission, the length of the frame to be transmitted must be programmed via the transmit byte count registers (xbch, xbcl). the resulting byte count equals the programmed value plus one byte. since 12 bits are provided via xbch, xbcl (xbc11 ? xbc0) a frame length between 1 and 4096 bytes can be selected. having written the transmit byte counter registers, data transmission can be initiated by command xtf/xpd or xdd. the sacco will then autonomously request the correct amount of write bus cycles by activating the drqt-line. depending on the programmed frame length, block data transfers of n 32-bytes + remainder are requested every time the 32 byte transmit pool is accessible to the dma-controller. the following figure gives an example of a dma driven transmission sequence with a frame length of 70 bytes, i.e. programmed transmit byte count (xcnt) equal 69 bytes. figure 3-6 dma driven transmission example itd08036 6 32 32 serial interface sacco cpu interface wr 32 bytes transmit frame (70 bytes) xtf xpr wr xpr xpr command wr 6 bytes xtf xtf + xme 32 bytes itd05848 drqt (6) 6 32 32 wr serial interface sacco cpu interface wr wr drqt (32) xtf wr; xcnt = 69 transmit frame (70 bytes) xpr drqt (32) peb 20560 operational description semiconductor group 3-13 1997-11-01 3.1.4.3 data reception in interrupt mode in receive direction 2 32-byte fifo-buffers (receive pools) are also provided for each channel. there are two different interrupt indications concerned with the reception of data: C a rpf (receive pool full) interrupt indicates that a 32-byte block of data can be read from the rfifo with the received message not yet complete. C a rme (receive message end) interrupt indicates that the reception of one message is completed, i.e. either C one message with less than 32 bytes, or the C last part of a message with more than 32 bytes is stored in the cpu accessible part of the rfifo. the cpu must handle the rpf-interrupt before additional 32 bytes are received via the serial interface, as failure to do so causes a rdo (receive data overflow). status information about the received frame is appended to the frame in the rfifo. this status information follows the format of the rsta-register, unless using the sacco-a in clock mode 3. the cpu can read the length of the received message (including the appended receive status byte) from the rbch- and rbcl-registers. after the received data has been read from the rfifo, this must be explicitly acknowledged by the cpu issuing a rmc- (receive message complete) command! the following figure gives an example of an interrupt controlled reception sequence, supposing that a long frame (66 bytes) followed by a short frame (6 bytes) are received. figure 3-7 interrupt driven reception example itd05849 6 2 32 32 receive 66 bytes receive rmc rme byte count serial interface sacco cpu interface rme rfifo 7 bytes rmc 3 bytes rfifo count byte rpf rpf rfifo 32 bytes rfifo rmc rmc 6 bytes 32 bytes peb 20560 operational description semiconductor group 3-14 1997-11-01 3.1.4.4 data reception in dma-mode if the rfifo contains 32 bytes, the sacco autonomously requests a block dma- transfer by activating the drqr-line. this forces the dma-controller to continuously perform bus cycles until 32 bytes are transferred from the sacco to the system memory. if the rfifo contains less than 32 bytes (one short frame or the last part of a long frame) the sacco requests a block data transfer depending on the contents of the rfifo according to the following table: after the dma-controller has been set up for the reception of the next frame, the cpu must issue a rmc-command to acknowledge the completion of the receive frame processing. prior to the reception of this rmc, the sacco will not initiate further dma- cycles by activating the drqr-line. the following figure gives an example of a dma controlled reception sequence supposing that a long frame (66 bytes) followed by a short frame (6 byte) are received. figure 3-8 dma-driven reception example table 3-1 rfifo contents (in bytes) dma request (in bytes) 1, 2, 3 4 4, 5, 6, 7 8 8-15 16 16-32 32 itd05850 drqr (32) drqr (4) 6 2 32 32 receive 66 bytes receive rd rd rd rd rmc rme byte count (7) rme byte count (67) rmc serial interface sacco cpu interface 68 dma read cycles 6 bytes drqr (32) drqr (8) peb 20560 operational description semiconductor group 3-15 1997-11-01 3.1.5 d-channel arbiter the d-channel arbiter links the sacco-a to the cfi of the epic-1. epic-1 and sacco-a should therefore be initialized before setting up the d-channel arbiter, as demonstrated in chapter 3.1.6 . in downstream direction, the d-channel arbiter distributes data from the sacco-a to the selected subscribers. in upstream direction, the d-channel arbiter ensures that the sacco-a receives data from only a single correspondent at a time. given proper initialization, the operation of the d-channel arbiter is largely transparent. the user of the elic can thus concentrate on operating the sacco-a as described in chapters 2.1.2.5 and 3.1.4 . for the d-channel arbiter to operate as desired, the sacco-a must be set clock mode 3 and inter frame timefill set to all 1s. it is also recommended that the sacco-a not be set into auto-mode when communicating with downstream subscribers. the epic-1s cfi should be configured to follow the line card iom-2 protocol, i.e.: C cfi mode 0 C 2-mbit/s data rate (usually with a double rate clock) C 256 bits per frame and port (8 subscribers per port) C 16-kbit/s d-channels positioned as bits 7,6 of time-slots (n 4) - 1 for n = 1 ? 8 3.1.5.1 sacco - a transmission sending data from the sacco-a to downstream subscribers is handled by the transmit channel master of the d-channel arbiter. the downstream control memory (cm) code for subscribers who may be sent data by the sacco-a must be set to 1010 b for the even time-slot and to 1011 b for the odd time-slot. the cm-data of the even time-slot should be programmed to 11 c/i-code 11. for example, a cm-data entry of 11000011 would set the c/i-code to 0000. refer to figure 3-3 . if data is to be sent to a single subscriber (no broadcasting), this subscriber must be selected in the xdc-register. whenever the subscribers d-channel is to be output at the elics cfi, the transmit channel master provides a 2-bit transmit strobe to the sacco-a. every frame, 2 data bits are thus strobed from the sacco-a into the subscribers d-channel, when the sacco-a has been commanded to send data. as the subscribers d-channel recurs every 125 m s, the data is transmitted from the sacco-a to the subscriber at a rate of 16 kbit/s. if the sacco-a has no data to send, it sends its inter frame timefill (1s) to the subscriber when strobed by the transmit channel master. with the xdc.bct bit set (broadcasting), the bcg-registers are used to select the subscribers to whom the saccos data is to be sent. the saccos output is first copied to an internal buffer. from this buffer, the data is strobed, 2 bits at a time, to all selected subscribers. when the sacco-a has no data to send, its inter frame timefill (1s) is copied to the buffer and strobed into the d-channels of the selected subscribers. peb 20560 operational description semiconductor group 3-16 1997-11-01 3.1.5.2 sacco - a reception subscribers who are to participate in the d-channel arbitration for the sacco-a must send all 1s as inter frame timefill of their d-channels. flags or idle codes other than all 1s are not permitted as inter frame timefill. for any participating subscriber, the blocked code must be programmed into the downstream control memory (cm). also, the subscribers d-channel must be enabled in the dce-register. in the full selection state, the d-channel arbiter overwrites the downstream blocked code of enabled subscribers with the available code. on the upstream cfi-input lines, the d-channel arbiter monitors all d-channels enabled in the dce-registers. when the d-channel arbiter detects a 0 on any monitored d-channel it assumes this to be the start of an opening flag. it therefore strobes the d-channel data of this subscriber to the sacco-a and starts the suspend counter. for this selected subscriber, the d-channel arbiter continues to overwrite the downstream blocked code with the available code. however, all other enabled subscribers are now passed the blocked code from the downstream cm. if the sacco-a does indeed receive an hdlc-frame C complete or aborted C from the selected subscriber, the suspend counter is reset. while the sacco-a receives data from the selected subscriber, the blocked code stops all other subscribers from sending data to the sacco-a. after the sacco-a has received a closing flag or abort sequence for the subscribers frame, the d-channel arbiter stops strobing the subscribers data to the sacco-a and enters the limited selection state. if, after the initial 0, the sacco-a does not receive an hdlc-frame C complete or aborted C from the selected subscriber, it does not reset the suspend counter. eventually, the suspend counter under flows, setting off the ista.ida-interrupt. the subscriber who sent the erroneous 0 can then be identified in the astate-register. any subscriber who frequently sends erroneous 0s should be disabled from the dce, and the cause of the error investigated. after the ista.ida-interrupt, the sacco-a receiver must be reset to resume operation in the full selection state. the limited selection state is identical to the full selection state, except that the subscriber who last sent data to the sacco-a is excluded from the arbitration. this prevents any single subscriber from constantly keeping the sacco-a busy. the blocked code of the cm is passed to the excluded subscriber, while the d-channel arbiter sends all other enabled subscribers the available code. all enabled subscribers C except the one excluded C are monitored for the starting 0 of an opening flag. how long the exclusion lasts can be programmed in the amo-register. if none of the monitored subscribers has started sending data during this time, the d-channel arbiter re-enters the full selection state. peb 20560 operational description semiconductor group 3-17 1997-11-01 3.1.6 initialization procedure for proper initialization of the doc the following procedure is recommended: 3.1.6.1 hardware reset refer to chapter 2.1.2.2 reset logic. 3.1.6.2 epic ? -1 initialization 3.1.6.2.1 epic ? registers initialization the pcm- and cfi-configuration registers (pmod, pbnr, ? , cmd1, cmd2, ? ) should be programmed to the values required for the application. the correct setting of the pcm- and cfi-registers is important in order to obtain a reference clock (rcl) which is consistent with the externally applied clock signals. the state of the operation mode (omdr:oms10 bits) does not matter for this programming step. pmod = pcm-mode, timing characteristics, etc. pbnr = number of bits per pcm-frame pofd = pcm-offset downstream pofu = pcm-offset upstream pcsr = pcm-timing cmd1 = cfi-mode, timing characteristics, etc. cmd2 = cfi-timing cbnr = number of bits per cfi-frame ctar = cfi-offset (time-slots) cbsr = cfi-offset (bits) cscr = cfi-sub channel positions 3.1.6.2.2 control memory reset since the hardware reset does not affect the epic-1 memories (control and data memories), it is mandatory to perform a software reset of the cm. the cm-code 0000 (unassigned channel) should be written to each location of the cm. the data written to the cm-data field is then dont care, e.g. ff h . omdr:oms10 must be to 00 b for this procedure (reset value). madr = ff h macr = 70 h wait for epic.star:mac = 0 the resetting of the complete cm takes 256 rcl-clock cycles. during this time, the epic.star:mac-bit is set to logical 1. peb 20560 operational description semiconductor group 3-18 1997-11-01 3.1.6.2.3 initialization of pre-processed channels after the cm-reset, all cfi time-slots are unassigned. if the cfi is used as a plain pcm- interface, i.e. containing only switched channels (b-channels), the initialization steps below are not required. the initialization of pre-processed channels applies only to iom- or sld-applications. an iom- or sld- channel consists of four consecutive time-slots. the first two time-slots, the b-channels need not be initialized since they are already set to unassigned channels by the cm-reset command. later, in the application phase of the software, the b-channels can be dynamically switched according to system requirements. the last two time-slots of such an iom- or sld-channel, the pre-processed channels must be initialized for the desired functionality. there are five options that can be selected: also refer to figure 3-4 . example in cfi-mode 0 all four cfi-ports shall be initialized as iom-2 ports with a 4-bit c/i-field and d-channel handling by the sacco-a. cfi time-slots 0, 1, 4, 5, 8, 9 ? 28, 29 of each port are b-channels and need not to be initialized. table 3-2 pre-processed channel options at the cfi even cfi time-slot odd cfi time-slot main application monitor/feature control channel monitor/feature control channel monitor/feature control channel monitor/feature control channel monitor/feature control channel 4-bit c/i-channel, d-channel handled by sacco-a and d-ch. arbiter 4-bit c/i-channel, d-channel not switched (decentral d-ch. handling) 4-bit c/i-channel, d-channel switched (central d-ch. handling) 6-bit sig-channel 8-bit sig/channel iom-1 or iom-2 digital subscriber iom-1 or iom-2 digital subscriber iom-1 or iom-2 digital subscriber iom-2, analog subscriber sld, analog subscriber peb 20560 operational description semiconductor group 3-19 1997-11-01 cfi time-slots 2, 3, 6, 7, 10, 11 ? 30, 31 of each port are pre-processed channels and need to be initialized: cfi-port 0, time-slot 2 (even), downstream madr = ff h ; the c/i-value 1111 will be transmitted upon cfi-activation maar = 08 h ; addresses ts 2 down macr = 7a h ; cm-code 1010 wait for star:mac = 0 cfi-port 0, time-slot 3 (odd), downstream madr = ff h ; dont care maar = 09 h ; addresses ts 3 down macr = 7b h ; cm-code 1011 wait for star:mac = 0 cfi-port 0, time-slot 2 (even), upstream madr = ff h ; the c/i-value 1111 is expected upon cfi-activation maar = 88 h ; address ts 2 up macr = 78 h ; cm-code 1000 wait for star:mac = 0 cfi-port 0, time-slot 3 (odd), upstream madr = ff h ; dont care maar = 89 h ; address ts 3 up macr = 70 h ; cm-code 0000' wait for star:mac = 0 repeat the above programming steps for the remaining cfi-ports and time-slots. this procedure can be speeded up by selecting the cm-initialization mode (omdr:oms10 = 10). if this selection is made, the access time to a single memory location is reduced to 2.5 rcl-cycles. the complete initialization time for 32 iom-2 channels is then reduced to 128 0.61 m s = 78 m s. 3.1.6.2.4 initialization of the upstream data memory (dm) tri-state field for each pcm time-slot the tri-state field defines whether the contents of the dm-data field are to be transmitted (low impedance), or whether the pcm time-slot shall be set to high impedance. the contents of the tri-state field is not modified by a hardware reset. in order to have all pcm time-slots set to high impedance upon the activation of the pcm- interface, each location of the tri-state field must be loaded with the value 0000. for this purpose, the tri-state reset command can be used: peb 20560 operational description semiconductor group 3-20 1997-11-01 omdr = c0 h ; oms10 = 11, normal mode madr = 0 0 h ; code field value 0000 b macr = 68 h ; moc-code to initialize all tri-state locations (1101 b ) wait for star:mac = 0 the initialization of the complete tri-state field takes 1035 rcl-cycles. note: 1) it is also possible to program the value 1111 to the tri-state field in order to have all time-slots switched to low impedance upon the activation of the pcm-interface. 2) while omdr:psb = 0, all pcm-output drivers are set to high impedance, regardless of the values written to the tri-state field. 3.1.6.3 sacco-initialization to initialize the sacco, the cpu has to write a minimum set of registers. depending on the operating mode and on the features required, an optional set of register must also be initialized. as the first register to be initialized, the mode-register defines operating and address mode. if data reception shall be performed, the receiver must be activated by setting the rac-bit. depending on the mode selected, the following registers must also be defined: the second minimum register to be initialized is the ccr2. in combination with the ccr1, the ccr2 defines the configuration of the serial port. it also allows enabling the rfs-interrupt. if bus configuration is selected, the external serial bus must be connected to the c d-pin for collision detection. in point-to-point configuration, the c d-pin must be tied to ground if no clear to send function is provided via a modem. table 3-3 mode dependent register set-up 1 byte address 2 byte address transparent mode 1 rah1 rah2 non-auto mode rah1 = 00 h rah2 = 00 h ral1 ral2 rah1 rah2 ral1 ral2 auto-mode xad1 xad2 rah1 = 00 h rah2 ral1 ral2 xad1 xad2 rah1 rah2 ral1 ral2 peb 20560 operational description semiconductor group 3-21 1997-11-01 depending on the features desired, the following registers may also require initializing before powering up the sacco: the ccr1 is the final minimum register that has to be programmed to initialize the sacco. in addition to defining the serial port configuration, the ccr1 sets the clock mode and allows the cpu to power-up or power-down the sacco. in power-down mode all internal clocks are disabled, and no interrupts are forwarded to the cpu. this state can be used as standby mode for reduced power consumption. switching between power-up or power-down mode has no effect on the contents of the register, i.e. the internal state remains stored. after power-up of the sacco, the cpu should bring the transmitter and receiver to a defined state by issuing a xres (transmitter reset) and rhr (receiver reset) command via the cmdr-register. the sacco will then be ready to transmit and receive data. the cpu controls the data transfer phase mainly by commands to the sacco via the cmdr-register, and by interrupt indications from the sacco to the cpu. status information that does not trigger an interrupt is constantly available in the star-register. 3.1.6.4 initialization of d-channel arbiter the d-channel arbiter links the sacco-a to the cfi of the epic-1 part of the elic. thus the epic-1 and sacco-parts of the elic should be initialized before initializing the d-channel arbiter. for subscribers wishing to communicate with the sacco-a, the correct pre-processed channel code must have been programmed in the epic-1s control memory. in downstream direction, this code is cmc = 1010 for the even time-slot and cmc = 1011 for the odd time-slot. in upstream direction, any pre-processed channel code is also valid for arbiter operation. this is shown in figure 3-3 of chapter 3.1.3.3 . for an example refer to chapter 3.1.6.2.3 . if the mr-bit is used to block downstream subscribers, the blocking code mr = 0 b can be written as madr = 11xxxx01 b when initializing the even downstream time-slot. the x stand for the c/i-code. this also is shown in figure 3-3 . if the c/i-code is used to block downstream subscribers, such subscribers must be activated with the c/i-code 1100 b , not 1000 b . table 3-4 feature dependent register set-up feature register(s) clock mode 2 tsar, tsac, xccr, rccr masking selected interrupts mask dma controlled data transfer xbch check on receive length rlcr peb 20560 operational description semiconductor group 3-22 1997-11-01 the sacco-a must be initialized to clock mode 3 to communicate with downstream subscribers. in clock mode 3, the sacco-a receives its input and transmit its output via the d-channel arbiter. if the ccr2.t de-bit is set, the sacco-as output is transmitted at the t da-pin in addition to being transmitted via the d-channel arbiter. once epic-1 and sacco-a have been correctly initialized, writing the subscribers address into the xdc-register allows the sacco-a to send the subscriber data. by setting the xdc.bct-bit and programming the bcg-registers, the sacco-a can transmit its data to several subscribers. to strobe upstream data from the cfi-interface to the sacco-as receiver, the amo- register must be programmed for the desired functionality. subscribers who are to be allowed to send data must be enabled via the dce-registers. if a subscriber tries to send data during the initialization of the upstream d-channel arbiter, a ista.ida-interrupt may occur. this interrupt can be cleared by resetting the sacco-a receiver. note: 1) the epic-1 and sacco-a must be initialized correctly before the d-channel arbiter can operate properly. particular care must be given to programming the epic-1s control memory (cm) with the required cm-codes (cmcs). 2) the upstream and downstream d-channel arbiter initializations are independent of each other. 3.1.6.5 activation of the pcm- and cfi-interfaces with epic-1, sacco-a and d-channel arbiter all configured to the system requirements, the pcm- and cfi-interface can be switched to the operational mode. the omdr:oms10 bits must be set (if this has not already be done) to the normal operation mode (oms10 = 11). when doing this, the pcm-framing interrupt (ista:pfi) will be enabled. if the applied clock and framing signals are in accordance with the values programmed to the pcm-registers, the pfi-interrupt will be generated (if not masked). when reading the status register, the star:pss-bit will be set to logical 1. to enable the pcm-output drivers set omdr:psb = 1. the cfi-interface is activated by programming omdr:csb = 1. this enables the output clock and framing signals (dcl and fsc), if these have been programmed as outputs. it also enables the cfi-output drivers. the output driver type can be selected between open drain and tri-state with the omdr:cos-bit. example: activation of the epic-1 part of the elic for a typical iom-2 application: omdr = ee h ; normal operation mode (oms10 = 11) pcm-interface active (psb = 1) pcm-test loop disabled (ptl = 0) cfi-output drivers: open drain (cos = 1) monitor handshake protocol selected (mfps = 1) cfi active (csb = 1) access to epic-1 registers via address pins a4a0 (rbs = 0) peb 20560 operational description semiconductor group 3-23 1997-11-01 3.1.6.6 initialization example in this sample initialization the elic is set up to handle a digital iom-2 subscriber. the interfaces of the doc/elic are shown below: figure 3-9 doc/elic ? interfaces for initialization example the subscriber uses the elics cfi-port 0, channel 0 (time-slots 0-3). the subscribers upstream b 1 -channel is to be switched to pcm-port 0, time-slot 5. the subscribers upstream b 2 -channel is to be looped back to the subscriber on the downstream b 1 -channel. the subscribers downstream b 2 -channel is to be switched from pcm-port 0, time-slot 1. the subscribers hdlc-data is exchanged via the d-channel with the sacco-a. monitor and c/i-channels are to be handled via the elic. the sacco-b communicates via a dedicated signaling highway with a non-pbc group controller. a 4-mhz clock is input as pdc and hdcb. port 1 of the elic is to be used as active low output. thus the port should be linked to pull-up resistors. write pcon1 = ff h write port1 = ff h its05808 epic r d channel controlling arbiter sacco ch-a sacco ch-b elic r p d channel highway b channels highway signaling pcm interface iom -2 r peb 20560 operational description semiconductor group 3-24 1997-11-01 3.1.6.6.1 epic ? -1 initialization example configure pcm-side of elic: write pmod = 44 h pcm-mode 1, single clock rate, pfs evaluated with falling edge of pdc, r d0 = logical input port 0 write pbnr = ff h 512 bits per pcm-frame write pofd = f0 h the internal pfs marks downstream bit 6, ts 0 (second bit of frame) write pofu = 18 h the internal pfs marks upstream bit 6, ts 0 (second bit of frame) write pcsr = 45 h no clock shift; pcm-data sampled with falling, transmitted with rising pdc configure cfi-side of elic: write cmd1 = 20 h pdc and pfs used as clock and framing source for the cfi; crcl = pdc; cfi-mode 0 write cmd2 = d0 h fsc shaped for iom-2 interface; dcl = 2 data rate; cfi-data received with falling, transmitted with rising crcl write cbnr = ff h 256 bits per cfi-frame write ctar = 02 h pfs is to mark cfi time-slot 0 write cbsr = 20 h pfs is to mark bit 7 of cfi time-slot 0; no shift of cfi-upstream data relative to cfi-downstream data write cscr = 00 h 2-bit channels located in position 7, 6 on all cfi-ports reset epic-1 control memory (cm) to ff h : write madr = ff h write macr = 70 h initialize epic-1 cm: write omdr = 80 h set epic-1 from cm-reset mode into cm-initialization mode the subscribers upstream b 1 -channel is switched to pcm-port 0, time-slot 5 write madr = 89 h connection to pcm-port 0, time-slot 5 write maar = 80 h from upstream cfi-port 0, time-slot 0 write macr = 71 h write cm-data addressed by maar with content of madr; write cm-code addressed by maar with 0001 b (code for a simple 64-kbit/s connection) read star wait for star:mac = 0 the subscribers upstream b 2 -channel is internally looped via pcm-port 1, time-slot 1 write madr = 85 h loop to pcm-port 1, time-slot 1 write maar = 81 h from upstream cfi-port 0, time-slot 1 write macr = 71 h write cm-data addressed by maar with content of madr; write cm-code addressed by maar with 0001 b (code for a simple 64 kbit/s connection) read star wait for star:mac = 0 peb 20560 operational description semiconductor group 3-25 1997-11-01 the subscribers upstream time-slots 2 and 3 are initialized as monitor and c/i-channels with decentral d-channel handling write madr = ff h received c/i-code to be compared to 1111 b write maar = 88 h from upstream cfi-port 0, time-slot 2 write macr = 78 h write cm-data addressed by maar with content of madr; write cm-code addressed by maar with 1000 b (even address code for decentral monitor and c/i-channels) read star wait for star:mac = 0 write maar = 89 h from upstream cfi-port 0, time-slot 3 write macr = 70 h write cm-code addressed by maar with 0000 b (odd address code for decentral monitor and c/i-channels) read star wait for star:mac = 0 the subscribers downstream b 1 -channel is internally looped via pcm-port 1, time-slot 1 write madr = 85 h internal loop from pcm-port 1, time-slot 1 write maar = 00 h to downstream cfi-port 0, time-slot 0 write macr = 71 h write cm-data addressed by maar with content of madr; write cm-code addressed by maar with 0001 b (code for a simple 64-kbit/s connection) read star wait for star:mac = 0 the subscribers downstream b 2 -channel is switched from pcm-port 0, time-slot 1 write madr = 01 h connection from pcm-port 0, time-slot 1 write maar = 01 h to downstream cfi-port 0, time-slot 1 write macr = 71 h write cm-data addressed by maar with content of madr; write cm-code addressed by maar with 0001 b (code for a simple 64-kbit/s connection) read star wait for star:mac = 0 the subscribers downstream time-slots 2 and 3 are initialized as monitor and c/i-channels with d-channel handling by the sacco-a write madr = ff h c/i-code to be transmitted = 1111 b (madr = f3 h d-channel blocking code 1100 b to be transmitted.) write maar = 08 h to downstream cfi-port 0, time-slot 2 write macr = 7a h write cm-data addressed by maar with content of madr; write cm-code addressed by maar with 1010 b (even address code for monitor and c/i-channels with d-channel handling by sacco-a) read star wait for star:mac = 0 write maar = 09 h from upstream cfi-port 0, time-slot 3 write macr = 7b h write cm-code addressed by maar with 1011 b (odd address code for monitor and c/i-channels with d-channel handling by sacco-a) read star wait for star:mac = 0 peb 20560 operational description semiconductor group 3-26 1997-11-01 set epic-1 to normal mode write omdr = c0 h set epic-1 to cm-normal mode; interrupt line will go active read ista = 20 h epic-1 interrupt read ista_e = 08 h pfi-interrupt: pcm-synchronisity status has changed read star_e = 25 h elic is synchronized to pcm-interface; mfifo ready reset tri-state field of data memory (dm) write madr = 00 h all bits of time-slot set to high impedance write macr = 68 h write madr to all locations of pcm-tri-state field read star wait for star:mac = 0 3.1.6.6.2 sacco - a initialization example configure the sacco-a for communication with downstream subscribers write mode = a8 h set sacco-b to transparent mode 1; switch receiver active write rah1 = 00 h response sapi1: signaling data write rah2 = 40 h response sapi 2: packet-switched data (write ccr2 = 00 h ) reset value: t da pin disabled; standard data sampling; rfs-interrupt disabled write ccr1 = 87 h power-up sacco-a in point to point configuration and clock mode 3 with double rate clock; inter frame timefill = all 1s reset the sacco-as fifos write cmdr = c1 h reset cpu accessible and cpu inaccessible part of rfifo, and reset xfifo; the interrupt line will go active read ista = 02 h interrupt of sacco-a read ista_a = 10 h transmit pool ready 3.1.6.6.3 d-channel arbiter initialization example enable d-channel transmission to cfi-port 0, channel 0 (write xdc = 00 h ) reset value: broadcasting disabled; transmit to channel 0 of port 0 enable d-channel reception on cfi-port 0, channel 0 write amo = f9 h start with maximum selection delay; suspend counter active; control of d-channel to take place via c/i-bit; control channel master enabled write dce0 = 01 h enable cfi-port 0, channel 0 for data reception peb 20560 operational description semiconductor group 3-27 1997-11-01 3.1.6.6.4 pcm- and cfi-interface activation example write omdr = ee h see chapter 3.1.6.5 . enable upstream pcm-port 0, time-slot 5 write madr = 0f h set all bits of time-slot to low impedance write maar = 89 h pcm-port 0, time-slot 5 write macr = 60 h write only single tri-state control position read star wait for star:mac = 0 3.1.6.6.5 sacco - b initialization example configure the sacco-b as secondary station for an upstream (non-pbc) group controller write mode = 48 h set sacco-b to 8-bit non-auto mode; switch receiver active write rah1 = 00 h the high-byte comparison registers should be set to 00 h when using non-auto mode write rah2 = 00 h write ral1 = 89 h 8-bit address of sacco-b write ral2 = ff h 8-bit group address (broadcast by group controller) write ccr2 = 08 h txdb pin enabled; standard data sampling; rfs-interrupt disabled write ccr1 = 98 h power-up sacco-b in point-to-point configuration and clock mode 0 with single rate clock; inter frame timefill = flags; t db is push-pull output reset the sacco-bs fifos write cmdr = c1 h reset cpu accessible and cpu inaccessible part of rfifo, and reset xfifo; the interrupt line will go active read ista = 08 h interrupt of sacco-b read ista_b = 10 h transmit pool ready peb 20560 operational description semiconductor group 3-28 1997-11-01 3.2 sidec the sidec is a 4-channel signaling controller containing sliphtly sacco modules and a control logic for drdy handling (stop/go signal from quat-s). to initialize one of the sidecs, the cpu has to write a minimum set of registers. depending on the operating mode and on the features required, an optional set of registers must also be initialized. as the first register to be initialized, the mode-register defines operating and address mode. if data reception shall be performed, the receiver must be activated by setting the rac-bit. depending on the mode selected, the following registers must also be defined: the second minimum register to be initialized is the ccr2. in combination with the ccr1, the ccr2 defines the configuration of the serial port. it also allows enabling the rfs-interrupt. another function of ccr2 is to define the operating mode for the d-channel ready input (drdy). depending on the features desired, the following registers may also require initializing before powering up the sidec: table 3-5 mode dependent register set-up 1 byte address 2 byte address transparent mode 1 rah1 rah2 non-auto mode rah1 = 00 h rah2 = 00 h ral1 ral2 rah1 rah2 ral1 ral2 auto-mode xad1 xad2 rah1 = 00 h rah2 ral1 ral2 xad1 xad2 rah1 rah2 ral1 ral2 table 3-6 feature dependent register set-up feature register(s) time-slot assignment tsar, tsac, xccr, rccr masking selected interrupts mask check on receive length rlcr peb 20560 operational description semiconductor group 3-29 1997-11-01 the ccr1 is the final minimum register that has to be programmed to initialize the sidec. in addition to defining the serial port configuration, the ccr1 defines the characteristic of all iom-2 ports allows the cpu to power-up or power-down a sidec. in power-down mode all internal clocks are disabled, and no interrupts are forwarded to the cpu. this state can be used as standby mode for reduced power consumption. switching between power-up or power-down mode has no effect on the contents of the register, i.e. the internal state remains stored. after power-up of the sidec, the cpu should bring the transmitter and receiver to a defined state by issuing a xres (transmitter reset) and rhr (receiver reset) command via the cmdr-register. the sidec will then be ready to transmit and receive data. the cpu controls the data transfer phase mainly by commands to the sidec via the cmdr-register, and by interrupt indications from the sidec to the cpu. status information that does not trigger an interrupt is constantly available in the star-register. peb 20560 dsp core oak semiconductor group 4-1 1997-11-01 4 dsp core oak 4.1 introduction 4.1.1 general description oak dsp core is a 16-bit (data and program) busses high performance fixed-point dsp core. oak is designed for the mid to high-end telecommunications and consumer electronics applications, where low-power and portability are still major requirements. among the applications supported by oak are not only pbx but also digital cellular telephones (like jdc, gsm, usdc), fast modems (like v.fast), advanced fax machines, etc. oak is aimed at achieving the best cost-performance factor for a given (small) silicon area. taking into account all elements of system-on-chip requirements, like: program size, data memory size, glue logic, power management, etc. based on the proven philosophy of its predecessor spc, oak is also designed to be used as an engine for dsp-based application specific ics. it is specified with several levels of modularity, in ram, rom, and i/o, allowing efficient dsp-based asic development. the core consists of the main blocks of a high performance central processing unit, including a full featured bit-manipulation unit, ram and rom addressing units, and program control logic. all other peripheral blocks, which are application specific, are defined as part of the user specified logic implemented around the oak core on the same silicon die. oak has an improved set of dsp and general microprocessor functions to meet the applications requirements. the oak programming model and instruction-set is aimed at straightforward generation of efficient and compact code. it has an enhanced instruction set which is upward compatible with the spc instruction set. oak also features a wide range of operating voltage, down to 2.7 v. oak is available as a core in a standard cell library, to be utilized as a part of the users custom chip design. oak is the second member in a family of standard dsp core cells. 4.1.2 architecture highlights the oak dsp core architecture is based on its predecessor spc. in the following description, the oak new features are bold-faced . the oak core consists of four parallel execution units: ? the computation unit (cu) ? the bit manipulation unit (bmu) , ? the data addressing arithmetic unit (daau), ? the program control unit (pcu). it has two blocks of data ram/rom for parallel feeding of the two inputs of the multiplier. peb 20560 dsp core oak semiconductor group 4-2 1997-11-01 the cu has a 16 by 16 bit multiplier (which performs signed by signed, signed by unsigned or unsigned by unsigned multiplications) supporting single and double precision multiplication. the cu has also a 36-bit alu, and two 36-bit accumulators with access to the two additional accumulators of the bmu. the bmu consists of a full 36-bit barrel shifter, a bit-field operations (bfo) unit including a special hardware for exponent calculation, and two 36-bit accumulators with access to the two accumulators of the cu. context switching (swapping) between the two sets of accumulators is supported. the daau, the pcu, the data and program memory organization, and buses structure are basically similar to those of spc. powerful zero-overhead looping, enables four levels of block-repeat (bkrep), in addition to an interruptable single word repeat. the pipeline structure has been improved to achieve minimal cycle time. an index-based addressing capability was added. shadow registers for parts of the status registers and alternative bank of registers for four of the daau registers were added to improve interrupt handling and subroutine nesting. option for automatic context switching during interrupts is also included. the hardware stack of spc is substituted with a more flexible software stack residing in the data memory space. this improvement, as well as the indexed-based addressing capability and the additional accumulators, will also support a c-compiler implementation for oak. an additional maskable interrupt has been added to the core and a nmi interrupt (used in spc for emulation by the name bpi) was released to the user as a non-maskable interrupt. for emulation support a breakpoint interrupt (bi) was added, sharing the same interrupt vector of trap. the core is designed to interface with external memories and peripherals having different speeds, using a wait-state mechanism. it supports dma mode and hold mode operation. it also has support for an automatic boot procedure, and it has support for on-chip emulation module, residing off-core. peb 20560 dsp core oak semiconductor group 4-3 1997-11-01 4.2 architecture features 4.2.1 features ? 16-bit fixed-point dsp core with high level of modularity: C expandable internal program rom. C expandable internal data ram and/or rom. C user-defined registers. ? 16 16 bit 2s complement parallel multiplier with 32-bit product. multiplication of signed by signed, signed by unsigned, and unsigned by unsigned. ? single cycle multiply-accumulate instructions. ? 36-bit alu. ? 36-bit left/right barrel shifter. ? four 36-bit accumulators. ? memory organization: ? 64 k word maximum addressable data space, organized in: local and external data memory space. C 64 k word maximum program memory space. C data rams can also be viewed as a single continuous ram. C user definable data rom on the same address space of the data ram. C alternative registers bank for 3 of the daau pointers (and 1 configuration register) with individual selectable bank exchanging. ? software stack (with stack pointer) residing in the data ram. ? index-based addressing capability. ? automatic context switching by interrupts (with enable/disable feature for each interrupt) using shadow registers for parts of status registers and swapping between two 36-bit accumulators. ? all general and most special purpose registers are arranged as a global register set of 34 registers that can be referenced in most data moves and core operations. ? bit-field (up to 16 bits) operations (bfo): set, reset, change, test. these operations are executed directly on registers and data memory content, with no affect on accumulators content. ? single cycle exponent evaluation of up to 36-bit values. ? enables full normalization operation in 2 cycles. ? double precision multiplication support. ? max/min single cycle instruction with pointer latching and modification. optimized for codebook search and viterbi decoding. ? single cycle division step support. ? single cycle data move & shift capability. ? arithmetic and logical shifting capability, according to a shift value stored in a special register, or embedded in the instruction opcode. conditional shift is also available, as well as rotate left and right operations. peb 20560 dsp core oak semiconductor group 4-4 1997-11-01 ? the product register is transferred to the accumulator without scaling, or after scaling by shifting the product 1 bit to the left, 2 bits to the left or 1 bit to the right. ? add/subtract/compare of a long immediate value with registers or data memory, with no affect on the accumulator content. ? powerful swapping (14 options) between two sets of accumulators. ? automatic saturation mode on overflow while reading content of accumulators, or using a special instruction. ? zero-overhead looping by two interruptable mechanisms: single word repeat and block repeat with four levels of nesting. ? memory mapped i/o. ? wait state support. ? support for program memory protection. ? upward compatibility with the spc instruction-set. ? on-chip emulation support. ? automatic boot procedure support. 4.2.2 buses 4.2.2.1 data buses data is transferred on the following 16-bit buses: two bidirectional buses - the x data bus (xdb); the internal core general data bus (gdb) and one unidirectional bus - the y data bus (ydb). the xdb is the main data bus, where most of the data transfers occur. it is a buffered extension of the internal general data bus (gdb). data transfer between the y data memory (yram) and the multiplier (y register) occurs over the ydb, when a multiply instruction uses two data memory location simultaneously. the bus structure supports register to register, register to memory, memory to register, program to data, program to register and data to program data movements. it can transfer up to two 16-bit words within one instruction cycle. addresses are specified for the local x_ram and y_ram on two unidirectional buses: the 16-bit x address bus (xab), and the 11-bit y address bus (yab). 4.2.2.2 program buses program memory addresses are specified on the 16-bit unidirectional program address bus (pab) while the instruction word fetches take place in parallel over program data bus (pdb). peb 20560 dsp core oak semiconductor group 4-5 1997-11-01 4.2.3 memory spaces and organization two independent memory spaces are available: the data space (xram and yram) and the program space. each of them is 64 k words. 4.2.3.1 program memory addresses 0x0000 - 0x0016 (see figure 4-1 ) are used as interrupt vectors for reset, trap/bi (software interrupt/breakpoint interrupt), nmi (non-maskable interrupt) and three maskable interrupts (int0, int1, int2). the reset, trap/bi and nmi vectors have been separated by two locations so that branch instructions can be accommodated in those locations if desired. the maskable interrupts have been separated by eight locations so that branch instructions, or small and fast interrupt service routines, can be accommodated in those locations. the program memory can be implemented on-chip, and/or off-chip. the oak supports a wait-state generator for interfacing slow program memory. the program memory addresses are generated by the pcu. figure 4-1 program memory map itd10231 h 0000 reset trap/b1 nmi interrupt 0 interrupt 1 interrupt 2 h 0002 h 0004 h 0006 h 000e h 0010 h ffff ~ ~ ~ ~ peb 20560 dsp core oak semiconductor group 4-6 1997-11-01 4.2.3.2 data memory the data space is divided into a y data space for the local yram, and a x data space for the xram. the xram space is divided into local data ram/rom of 1 k or 2 k, and an external space of 62 k or 60 k, respectively. the configuration is determined according to a core input pin. the local yram space and the local xram space were mapped to allow a continuous data space. the mapping is described in figure 4-2 . the data space partition allows expansion of the local xram and yram, and at the same time enables looking at the two rams as a single continuous data ram. the xram and yram can contain ram or rom. the x data memory can be expanded external (with no additional wait state cycles) up to the yram boundary. memory-mapped i/o is used, thus several addresses of the data space locations may be reserved for peripherals depending on the specific application configuration. wait states generation is possible. the external space, within the xram space, may contain slow memories and peripherals as well as fast memories and peripherals. when using slow memories, additional wait cycles have to be inserted. figure 4-2 data memory map for more details on oak architecture please refer to doc dsp programmers reference manual, 11.97 . 62 k words 1 k words 1 k words local xram 03ff 0000 h h 0400 h local external xram yram fbff h option 1 ffff fc00 h h 2 k words itd10228 07ff 0800 0000 h h h 60 k words 2 k words f800 f7ff h h option 2 ffff h peb 20560 dsp core oak semiconductor group 4-7 1997-11-01 4.3 development tools 4.3.1 coff macro assembler the coff macro assembler translates dsp assembly language source files into machine language object files. it consists of a macro pre-processor, has a complete programming restriction checking and prepares the object for full symbolic debugging. besides it is sensitive, contains c-like operators and conventions that allow easy development of code and data structures. the object files generated are compatible to the common object file format (coff). 4.3.2 linker/locator the linker/locator combines object files generated by the coff macro assembler into a single executable coff object file. as it creates the executable object file, it performs relocation which means map them to the target systems memory map. besides it supports user defined memory classes and enables to locate segments at absolute locations or relative to other segments and to overlay segments. the linking capability is very flexible and modular. 4.3.3 object format convertor most eprom programmers do not accept executable coff object files as input. therefore the object format converter translates the coff file into intel hex file format that can be downloaded to any ordinary eprom programmer. 4.3.4 ansi c-compiler the c-compiler is full featured ansi standard c-compiler which accepts c source code and produces assembler language source code, that can be processed by the coff marco assembler. it uses a sophisticated optimization pass that employs several advanced techniques for generating efficient, compact code from c source. beside the mixed language environment allows time critical routines to be replaced with very fast assembly routines for optimum performance with c language environment. both, in-line assembly and out-line assembly are supported. for stand alone applications, the compiler enables to link all code and initialization data into rom, allowing c code to run from reset. the c-compiler is fully integrated into the development environment, which allows the user complete control over c or assembly code during debugging. the compiler is based on the technology developed by the free software foundation (gnu). peb 20560 dsp core oak semiconductor group 4-8 1997-11-01 4.3.5 simulator the simulator simulates the operation for program verification and debugging purposes. it simulates the entire instruction set and accepts executable coff object code, generated from the linker/locator. the simulator allows verification and monitoring the dsp states without the requirement of hardware. besides a windowed, mouse driven interface which can be user customized, it also contains a high level language debug interface. to simulate external signals and hardware logic, it is possible to connect dos files and integrate c functions using the dynamic link library (dll) mechanism of windows. during program execution, the internal registers and memory of the simulated dsp are modified as each instruction is interpreted by the host. execution is suspended when either a breakpoint or an error is encountered or when the user halts execution. then the dsp internal registers and both program and data memory can be inspected and modified. 4.3.6 debugger to debug a program in realtime the simulator contains an emulation mode that directly interfaces to the on chip emulation module (ocem). compared with the simulation mode the user interface will be unchanged. all software development tools can be used on a standard pc. different tools are provided for win 3.1, win 95 and win nt. peb 20560 description of registers semiconductor group 5-1 1997-11-01 5 description of registers 5.1 m p address space register overview the following table contains an overview of all doc registers within the microprocessor address space. table 5-1 elic0 sacco-a reg name access address reset value comment page no. rfifo rd 000 h - 01f h xx h receive fifo 5-56 xfifo wr 000 h - 01f h xx h transmit fifo 5-57 ista rd 020 h 00 h int. status reg. 5-57 mask wr 020 h 00 h mask reg. 5-57 star rd 021 h 48 h status reg. 5-62 cmdr wr 021 h 00 h command reg. 5-59 mode rd/wr 022 h 00 h mode reg. 5-60 xad1 wr 024 h xx h transmit address 1 5-65 exir rd 024 h 00 h extended int. 5-58 xad2 wr 025 h x0 h transmit address 2 5-65 rbcl rd 025 h 00 h receive byte count low 5-67 rah1 wr 026 h xx h receive address high 1 5-67 rah2 wr 027 h xx h receive address high 2 5-67 rsta rd 027 h xx h receive status reg. 5-63 ral1 rd/wr 028 h xx h receive address low 1 5-66 ral2 wr 029 h xx h receive address low 2 5-66 rhcr rd 029 h xx h receive hdlc control byte 5-65 xbcl wr 02a h xx h transmit byte count low 5-84 ccr2 rd/wr 02c h 00 h channel config. reg. 2 5-62 rbch rd 02d h 000x h xxxx h receive byte count high 5-68 xbch wr 02d h 000x h xxxx h transmit byte count high 5-85 vstr rd 02e h 80 h version stat. reg. 5-68 rlcr wr 02e h xx h receive frame length check 5-62 ccr1 rd/wr 02f h 00 h channel config. reg. 1 5-61 peb 20560 description of registers semiconductor group 5-2 1997-11-01 tsax wr 030 h xx h time-slot assignment transmit 5-85 tsar wr 031 h xx h time-slot assignment receive 5-86 xccr wr 032 h 00 h transmit channel capacity 5-86 rccr wr 033 h 00 h receive channel cap. 5-86 table 5-2 elic0 sacco-b reg name access address reset value comment page no. rfifo rd 040 h - 05f h xx h receive fifo 5-56 xfifo wr 040 h - 05f h xx h transmit fifo 5-57 ista rd 060 h 00 h int. status reg. 5-57 mask wr 060 h 00 h mask reg. 5-57 star rd 061 h 48 h status reg. 5-62 cmdr wr 061 h 00 h command reg. 5-59 mode rd/wr 062 h 00 h mode reg. 5-60 xad1 wr 064 h xx h transmit address 1 5-65 exir rd 064 h 00 h extended int. 5-58 xad2 wr 065 h xx h transmit address 2 5-65 rbcl rd 065 h 00 h receive byte count low 5-67 rah1 wr 066 h xx h receive address high 1 5-67 rah2 wr 067 h xx h receive address high 2 5-67 rsta rd 067 h xx h receive status reg. 5-65 ral1 rd/wr 068 h xx h receive address low 1 5-66 ral2 wr 069 h xx h receive address low 2 5-66 rhcr rd 069 h xx h receive hdlc control byte 5-65 xbcl wr 06a h xx h transmit byte count low 5-67 ccr2 rd/wr 06c h 00 h channel config. reg. 2 5-62 rbch rd 06d h 000x h xxxx h receive byte count high 5-68 table 5-1 elic0 sacco-a (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-3 1997-11-01 xbch wr 06d h 000x h xxxx h transmit byte count high 5-85 vstr rd 06e h 80 h version stat. reg. 5-68 rlcr wr 06e h xx h receive frame length check 5-62 ccr1 rd/wr 06f h 00 h channel config. reg. 1 5-61 tsax wr 070 h xx h time-slot assignment transmit 5-85 tsar wr 071 h xx h time-slot assignment receive 5-86 xccr wr 072 h 00 h transmit channel capacity 5-86 rccr wr 073 h 00 h receive channel cap. 5-86 table 5-3 elic0-epic reg name access address reset value comment page no. macr rd/wr 080 h xx h memory acccess control register 5-38 maar rd/wr 081 h xx h memory acccess address register 5-42 madr rd/wr 082 h xx h memory acccess data register 5-43 stda rd/wr 083 h xx h synchron transfer data reg. a 5-43 stdb rd/wr 084 h xx h synchron transfer data reg. b 5-43 sara rd/wr 085 h xx h synchron transfer receive address reg. a 5-43 sarb rd/wr 086 h xx h synchron transfer receive address reg. b 5-44 saxa rd/wr 087 h xx h synchron transfer transmit address reg. a 5-45 saxb rd/wr 088 h xx h synchron transfer transmit address reg. b 5-45 table 5-2 elic0 sacco-b (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-4 1997-11-01 stcr rd/wr 089 h 00xx h xxxx h synchron transfer control reg. 5-46 mfair rd 08a h 0xxx h xxxx h mf-channel active indication reg. 5-47 mfsar wr 08a h 00 h mf-channel subscriber address reg. 5-47 mffifo rd/wr 08b h xx h mf-channel fifo 5-48 cififo rd 08c h 00 h signaling channel fifo 5-48 timr wr 08c h 00 h timer register 5-49 star_e rd 08d h o5 h status register epic 5-49 cmdr_e wr 08d h 00 h command register epic 5-50 ista_e rd 08e h 00 h interrupt status epic 5-52 mask_e wr 08e h 00 h mask register epic 5-53 omdr rd/wr 08f h 00 h operation mode register 5-54 pmod rd/wr 090 h 00 h pcm-mode register 5-26 pbnr rd/wr 091 h ff h pcm bit-number reg. 5-28 pofd rd/wr 092 h 00 h pcm-offset downstream register 5-28 pofu rd/wr 093 h 00 h pcm-offset upstream register 5-29 pcsr rd/wr 094 h 00 h pcm-clock shift register 5-29 picm rd 095 h xx h pcm-input comparison mismatch reg. 5-30 cmd1 rd/wr 096 h 00 h cfi-mode reg.1 5-30 cmd2 rd/wr 097 h 00 h cfi-mode reg. 2 5-33 cbnr rd/wr 098 h ff h cfi-bit number reg. 5-34 ctar rd/wr 099 h 00 h cfi time-slot adjustment register 5-35 cbsr rd/wr 09a h 00 h cfi-bit shift reg. 5-35 cscr rd/wr 09b h 00 h cfi-subchannel register 5-37 vnsr rd/wr 09d h 01 h version no. status register 5-56 table 5-3 elic0-epic (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-5 1997-11-01 table 5-4 elic0-mode register reg name access address reset value comment page no. emod rd/wr 0bf h xf h elic mode version no. 5-24 table 5-5 elic0-watch-dog timer reg name access address reset value comment page no. wtc rd/wr 0c0 h 1f h watchdog timer control reg. 5-23 table 5-6 elic0-interrupt top level reg name access address reset value comment page no. ista rd 0c1 h 00 h interrupt status register 5-22 mask wr 0c1 h 00 h mask register 5-23 table 5-7 elic0-arbiter reg name access address reset value comment page no. amo rd/wr 0e0 h 00 h arbiter mode register 5-87 astate rd 0e1 h xx h arbiter state register 5-87 scv rd/wr 0e2 h 00 h suspend counter value register 5-87 dce0 rd/wr 0e3 h 00 h d-channel enable reg. 0 5-89 dce1 rd/wr 0e4 h 00 h d-channel enable reg.1 5-89 dce2 rd/wr 0e5 h 00 h d-channel enable reg. 2 5-89 dce3 rd/wr 0e6 h 00 h d-channel enable reg. 3 5-89 xdc rd/wr 0e7 h 00 h transmit d-channel address register 5-90 bcg0 rd/wr 0e8 h 00 h broadcast group reg. 0 5-90 peb 20560 description of registers semiconductor group 5-6 1997-11-01 bcg1 rd/wr 0e9 h 00 h broadcast group reg. 1 5-90 bcg2 rd/wr 0ea h 00 h broadcast group reg. 2 5-90 bcg3 rd/wr 0eb h 00 h broadcast group reg. 3 5-91 table 5-8 elic1 sacco-a reg name access address reset value comment page no. rfifo rd 100 h - 11f h xx h receive fifo 5-56 xfifo wr 100 h - 11f h xx h transmit fifo 5-57 ista rd 120 h 00 h int. status reg. 5-57 mask wr 120 h 00 h mask reg. 5-57 star rd 121 h 48 h status reg. 5-62 cmdr wr 121 h 00 h command reg. 5-59 mode rd/wr 122 h 00 h mode reg. 5-60 xad1 wr 124 h xx h transmit address 1 5-65 exir rd 124 h 00 h extended int. 5-58 xad2 wr 125 h xx h transmit address 2 5-65 rbcl rd 125 h 00 h receive byte count low 5-67 rah1 wr 126 h xx h receive address high 1 5-67 rah2 wr 127 h xx h receive address high 2 5-67 rsta rd 127 h xx h receive status reg. 5-63 ral1 rd/wr 128 h xx h receive address low 1 5-66 ral2 wr 129 h xx h receive address low 2 5-66 rhcr rd 129 h xx h receive hdlc control byte 5-65 xbcl wr 12a h xx h transmit byte count low 5-84 ccr2 rd/wr 12c h 00 h channel config. reg. 2 5-62 rbch rd 12d h 000x h xxxx h receive byte count high 5-68 xbch wr 12d h 000x h xxxx h transmit byte count high 5-85 table 5-7 elic0-arbiter (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-7 1997-11-01 vstr rd 12e h 80 h version stat. reg. 5-68 rlcr wr 12e h xx h receive frame length check 5-62 ccr1 rd/wr 12f h 00 h channel config. reg. 1 5-61 tsax wr 130 h xx h time-slot assignment transmit 5-85 tsar wr 131 h xx h time-slot assignment receiver 5-86 xccr wr 132 h 00 h transmit channel capacity 5-86 rccr wr 133 h 00 h receive channel cap. 5-86 table 5-9 elic1 sacco-b reg name access address reset value comment page no. rfifo rd 140 h -15f h xx h receive fifo 5-56 xfifo wr 140 h -15f h xx h transmit fifo 5-57 ista rd 160 h 00 h int. status reg. 5-57 mask wr 160 h 00 h mask reg. 5-57 star rd 161 h 48 h status reg. 5-62 cmdr wr 161 h 00 h command reg. 5-59 mode rd/wr 162 h 00 h mode reg. 5-60 xad1 wr 164 h xx h transmit address 1 5-65 exir rd 164 h 00 h extended int. 5-58 xad2 wr 165 h xx h transmit address 2 5-65 rbcl rd 165 h 00 h receive byte count low 5-67 rah1 wr 166 h xx h receive address high 1 5-67 rah2 wr 167 h xx h receive address high 2 5-67 rsta rd 167 h xx h receive status reg. 5-65 ral1 rd/wr 168 h xx h receive address low 1 5-66 ral2 wr 169 h xx h receive address low 2 5-66 rhcr rd 169 h xx h receive hdlc control byte 5-65 xbcl wr 16a h xx h transmit byte count low 5-67 table 5-8 elic1 sacco-a (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-8 1997-11-01 ccr2 rd/wr 16c h 00 h channel config. reg. 2 5-62 rbch rd 16d h 000xxxxx h receive byte count high 5-68 xbch wr 16d h 000xxxxx h transmit byte count high 5-85 vstr rd 16e h 80 h version stat. reg. 5-68 rlcr wr 16e h xx h receive frame length check 5-62 ccr1 rd/wr 16f h 00 h channel config. reg. 1 5-61 tsax wr 170 h xx h time-slot assignment transmitter 5-85 tsar wr 171 h xx h time-slot assignment receiver 5-86 xccr wr 172 h 00 h transmit channel capacity 5-86 rccr wr 173 h 00 h receive channel cap. 5-86 table 5-10 elic1-epic reg name access address reset value comment page no. macr rd/wr 180 h xx h memory acccess control register 5-38 maar rd/wr 181 h xx h memory acccess address register 5-42 madr rd/wr 182 h xx h memory acccess data register 5-43 stda rd/wr 183 h xx h synchron transfer data reg. a 5-43 stdb rd/wr 184 h xx h synchron transfer data reg. b 5-43 sara rd/wr 185 h xx h synchron transfer receive address reg. a 5-44 sarb rd/wr 186 h xx h synchron transfer receive address reg. b 5-44 saxa rd/wr 187 h xx h synchron transfer transmit address reg. a 5-45 saxb rd/wr 188 h xx h synchron transfer transmit address reg. b 5-45 table 5-9 elic1 sacco-b (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-9 1997-11-01 stcr rd/wr 189 h 00xxxxxx h synchron transfer control reg. 5-46 mfair rd 18a h 0xxxxxxx h mf-channel active indication reg. 5-47 mfsar wr 18a h 00 h mf-channel subscriber address reg. 5-47 mffifo 18b h xx h mf-channel fifo 5-48 cififo rd 18c h 00 h signaling channel fifo 5-48 timr wr 18c h 00 h timer register 5-49 star_e rd 18d h o5 h status register epic 5-49 cmdr_e wr 18d h 00 h command register epic 5-50 ista_e rd 18e h 00 h interrupt status epic 5-52 mask_e wr 18e h 00 h mask register epic 5-53 omdr rd/wr 18f h 00 h operation mode register 5-54 pmod rd/wr 190 h 00 h pcm-mode register 5-26 pbnr rd/wr 191 h ff h pcm bit-number reg. 5-28 pofd rd/wr 192 h 00 h pcm-offset downstream register 5-28 pofu rd/wr 193 h 00 h pcm-offset upstream register 5-29 pcsr rd/wr 194 h 00 h pcm-clock shift register 5-29 picm rd 195 h xx h pcm-input comparison mismatch reg. 5-30 cmd1 rd/wr 196 h 00 h cfi-mode reg.1 5-30 cmd2 rd/wr 197 h 00 h cfi-mode reg. 2 5-33 cbnr rd/wr 198 h ff h cfi-bit number reg. 5-34 ctar rd/wr 199 h 00 h cfi time-slot adjustment register 5-35 cbsr rd/wr 19a h 00 h cfi-bit shift reg. 5-35 cscr rd/wr 19b h 00 h cfi-subchannel register 5-37 vnsr rd/wr 19d h 01 h version no. status register 5-56 table 5-10 elic1-epic (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-10 1997-11-01 table 5-11 elic1-mode register reg name access address reset value comment page no. emod rd/wr 1bf h xf h elic mode version no. 5-24 table 5-12 elic1-interrupt top level reg name access address reset value comment page no. ista rd 1c1 h 00 h interrupt status register 5-22 mask wr 1c1 h 00 h mask register 5-23 table 5-13 elic1-arbiter reg name access address reset value comment page no. amo rd/wr 1e0 h 00 h arbiter mode register 5-87 astate rd 1e1 h xx h arbiter state register 5-88 scv rd/wr 1e2 h 00 h suspend counter value register 5-88 dce0 rd/wr 1e3 h 00 h d-channel enable reg. 0 5-89 dce1 rd/wr 1e4 h 00 h d-channel enable reg.1 5-89 dce2 rd/wr 1e5 h 00 h d-channel enable reg. 2 5-89 dce3 rd/wr 1e6 h 00 h d-channel enable reg. 3 5-89 xdc rd/wr 1e7 h 00 h transmit d-channel address register 5-90 bcg0 rd/wr 1e8 h 00 h broadcast group reg. 0 5-90 bcg1 rd/wr 1e9 h 00 h broadcast group reg. 1 5-90 bcg2 rd/wr 1ea h 00 h broadcast group reg. 2 5-90 bcg3 rd/wr 1eb h 00 h broadcast group reg. 3 5-91 peb 20560 description of registers semiconductor group 5-11 1997-11-01 table 5-14 sidec0 reg name access address reset value comment page no. rfifo rd 200 h - 21f h xx h receive fifo 5-57 xfifo wr 200 h - 21f h xx h transmit fifo 5-57 ista rd 220 h 00 h int. status reg. 5-57 mask wr 220 h 00 h mask reg. 5-57 star rd 221 h 48 h status reg. 5-62 cmdr wr 221 h 00 h command reg. 5-59 mode rd/wr 222 h 00 h mode reg. 5-60 xad1 wr 224 h xx h transmit address 1 5-65 exir rd 224 h 00 h extended int. 5-58 xad2 wr 225 h xx h transmit address 2 5-65 rbcl rd 225 h 00 h receive byte count low 5-67 rah1 wr 226 h xx h receive address high 1 5-67 rah2 wr 227 h xx h receive address high 2 5-67 rsta rd 227 h xx h receive status reg. 5-63 ral1 rd/wr 228 h xx h receive address low 1 5-66 ral2 wr 229 h xx h receive address low 2 5-66 rhcr rd 229 h xx h receive hdlc control byte 5-65 xbcl wr 22a h xx h transmit byte count low 5-84 ccr2 rd/wr 22c h 00 h channel config. reg. 2 5-62 rbch rd 22d h 000x h xxxx h receive byte count high 5-68 xbch wr 22d h 000x h xxxx h transmit byte count high 5-85 vstr rd 22e h 80 h version stat. reg. 5-68 rlcr wr 22e h xx h receive frame length check 5-62 ccr1 rd/wr 22f h 00 h channel config. reg. 1 5-61 tsax wr 230 h xx h time-slot assignment transmit 5-85 tsar wr 231 h xx h time-slot assignment receiver 5-86 xccr wr 232 h 00 h transmit channel capacity 5-86 rccr wr 233 h 00 h receive channel cap. 5-86 peb 20560 description of registers semiconductor group 5-12 1997-11-01 table 5-15 sidec1 reg name access address reset value comment page no. rfifo rd 240 h - 25f h xx h receive fifo 5-57 xfifo wr 240 h - 25f h xx h transmit fifo 5-57 ista rd 260 h 00 h int. status reg. 5-57 mask wr 260 h 00 h mask reg. 5-57 star rd 261 h 48 h status reg. 5-62 cmdr wr 261 h 00 h command reg. 5-59 mode rd/wr 262 h 00 h mode reg. 5-60 xad1 wr 264 h xx h transmit address 1 5-65 exir rd 264 h 00 h extended int. 5-58 xad2 wr 265 h xx h transmit address 2 5-65 rbcl rd 265 h 00 h receive byte count low 5-67 rah1 wr 266 h xx h receive address high 1 5-67 rah2 wr 267 h xx h receive address high 2 5-67 rsta rd 267 h xx h receive status reg. 5-63 ral1 rd/wr 268 h xx h receive address low 1 5-66 ral2 wr 269 h xx h receive address low 2 5-66 rhcr rd 269 h xx h receive hdlc control byte 5-65 xbcl wr 26a h xx h transmit byte count low 5-84 ccr2 rd/wr 26c h 00 h channel config. reg. 2 5-62 rbch rd 26d h 000x h xxxx h receive byte count high 5-68 xbch wr 26d h 000x h xxxx h transmit byte count high 5-85 vstr rd 26e h 80 h version stat. reg. 5-68 rlcr wr 26e h xx h receive frame length check 5-62 ccr1 rd/wr 26f h 00 h channel config. reg. 1 5-61 tsax wr 270 h xx h time-slot assignment transmit 5-85 tsar wr 271 h xx h time-slot assignment receive 5-86 xccr wr 272 h 00 h transmit channel capacity 5-86 rccr wr 273 h 00 h receive channell capacity 5-86 peb 20560 description of registers semiconductor group 5-13 1997-11-01 table 5-16 sidec2 reg name access address reset value comment page no. rfifo rd 280 h - 29f h xx h receive fifo 5-57 xfifo wr 280 h - 29f h xx h transmit fifo 5-57 ista rd 2a0 h 00 h int. status reg. 5-57 mask wr 2a0 h 00 h mask reg. 5-57 star rd 2a1 h 48 h status reg. 5-62 cmdr wr 2a1 h 00 h command reg. 5-59 mode rd/wr 2a2 h 00 h mode reg. 5-60 xad1 wr 2a4 h xx h transmit address 1 5-65 exir rd 2a4 h 00 h extended int. 5-58 xad2 wr 2a5 h xx h transmit address 2 5-65 rbcl rd 2a5 h 00 h receive byte count low 5-67 rah1 wr 2a6 h xx h receive address high 1 5-67 rah2 wr 2a7 h xx h receive address high 2 5-67 rsta rd 2a7 h xx h receive status reg. 5-63 ral1 rd/wr 2a8 h xx h receive address low 1 5-66 ral2 wr 2a9 h xx h receive address low 2 5-66 rhcr rd 2a9 h xx h receive hdlc control byte 5-65 xbcl wr 2aa h xx h transmit byte count low 5-84 ccr2 rd/wr 2ac h 00 h channel config. reg. 2 5-62 rbch rd 2ad h 000x h xxxx h receive byte count high 5-68 xbch wr 2ad h 000x h xxxx h transmit byte count high 5-85 vstr rd 2ae h 80 h version stat. reg. 5-68 rlcr wr 2ae h xx h receive frame length check 5-62 ccr1 rd/wr 2af h 00 h channel config. reg. 1 5-61 tsax wr 2b0 h xx h time-slot assignment transmit 5-85 tsar wr 2b1 h xx h time-slot assignment receiver 5-86 xccr wr 2b2 h 00 h transmit channel capacity 5-86 rccr wr 2b3 h 00 h receive channell capacity 5-86 peb 20560 description of registers semiconductor group 5-14 1997-11-01 table 5-17 sidec3 reg name access address reset value comment page no. rfifo rd 2c0 h - 2df h xx h receive fifo 5-57 xfifo wr 2c0 h - 2df h xx h transmit fifo 5-57 ista rd 2e0 h 00 h int. status reg. 5-57 mask wr 2e0 h 00 h mask reg. 5-57 star rd 2e1 h 48 h status reg. 5-62 cmdr wr 2e1 h 00 h command reg. 5-59 mode rd/wr 2e2 h 00 h mode reg. 5-60 xad1 wr 2e4 h xx h transmit address 1 5-65 exir rd 2e4 h 00 h extended int. 5-58 xad2 wr 2e5 h xx h transmit address 2 5-65 rbcl rd 2e5 h 00 h receive byte count low 5-67 rah1 wr 2e6 h xx h receive address high 1 5-67 rah2 wr 2e7 h xx h receive address high 2 5-67 rsta rd 2e7 h xx h receive status reg. 5-63 ral1 rd/wr 2e8 h xx h receive address low 1 5-66 ral2 wr 2e9 h xx h receive address low 2 5-66 rhcr rd 2e9 h xx h receive hdlc control byte 5-65 xbcl wr 2ea h xx h transmit byte count low 5-84 ccr2 rd/wr 2ec h 00 h channel config. reg. 2 5-62 rbch rd 2ed h 000x h xxxx h receive byte count high 5-68 xbch wr 2ed h 000x h xxxx h transmit byte count high 5-85 vstr rd 2ee h 80 h version stat. reg. 5-68 rlcr wr 2ee h xx h receive frame length check 5-62 ccr1 rd/wr 2ef h 00 h channel config. reg. 1 5-61 tsax wr 2f0 h xx h time-slot assignment transmit 5-85 tsar wr 2f1 h xx h time-slot assignment receive 5-86 xccr wr 2f2 h 00 h transmit channel capacity 5-86 rccr wr 2f3 h 00 h receive channell capacity 5-86 peb 20560 description of registers semiconductor group 5-15 1997-11-01 table 5-18 icu reg name access address reset value comment page no. idoc rd/wr 300 h 00 h 2-131 ipc rd/wr 301 h 00 h 2-132 imaskr0 rd/wr 302 h ff h 2-129 imaskr1 rd/wr 303 h 07 h 2-130 ipar0 rd/wr 304 h 00 h 2-131 ipar1 rd/wr 305 h 00 h 2-131 ipar2 rd/wr 306 h 00 h 2-131 table 5-19 gpio reg name access address reset value comment page no. vcfgr rd/wr 320 h x0 h config. register (7-bit only) 2-157 vdatr rd/wr 321 h x0 h data register (4-bit only) 2-157 vnr rd 322 h x h version no. (4-bit read-only) 2-158 table 5-20 chi reg name access address reset value comment page no. vmodr rd/wr 323 h xxxx xooo mode reg. (3-bit only) 2-58 vdtr0 rd/wr 324 h xx h data reg. 0 2-59 vdtr1 rd/wr 325 h xx h data reg. 1 2-59 vdtr2 rd/wr 326 h xx h data reg. 2 2-59 vdtr3 rd/wr 327 h xx h data reg. 3 2-59 peb 20560 description of registers semiconductor group 5-16 1997-11-01 table 5-21 oak mail box reg name access address reset value comment page no. mcmd m p: wr oak: rd 340 h 00 h microprocessor command 2-117 mbusy oak: wr m p: rd 341 h 00 h microprocessor mail box busy 2-117 mdt0 (lsb) m p: wr oak: rd 342 h unchd microprocessor data reg. 0 2-117 mdt0 (msb) m p: wr oak: rd 343 h unchd 2-117 mdt1 (lsb) m p: wr oak: rd 344 h unchd microprocessor data reg.1 2-117 mdt1 (msb) m p: wr oak: rd 345 h unchd 2-117 mdt2 (lsb) m p: wr oak: rd 346 h unchd microprocessor data reg. 2 2-117 mdt2 (msb) m p: wr oak: rd 347 h unchd 2-117 mdt3 (lsb) m p: wr oak: rd 348 h unchd microprocessor data reg. 3 2-117 mdt3 (msb) m p: wr oak: rd 349 h unchd 2-117 mdt4 (lsb) m p: wr oak: rd 34a h unchd microprocessor data reg. 4 2-117 mdt4 (msb) m p: wr oak: rd 34b h unchd 2-117 mdt5 (lsb) m p: wr oak: rd 34c h unchd microprocessor data reg. 5 2-117 mdt5 (msb) m p: wr oak: rd 34d h unchd 2-117 ocmd m p: rd oak: wr 350 h 00 h oak command 2-117 obusy oak: rd m p: wr 351 h 00 h oak mail box busy 2-117 peb 20560 description of registers semiconductor group 5-17 1997-11-01 odt0 (lsb) m p: rd oak: wr 352 h unchd oak data reg. 0 2-117 odt0 (msb) m p: rd oak: wr 353 h unchd 2-117 odt1 (lsb) m p: rd oak: wr 354 h unchd oak data reg.1 2-117 odt1 (msb) m p: rd oak: wr 355 h unchd 2-117 odt2 (lsb) m p: rd oak: wr 356 h unchd oak data reg. 2 2-117 odt2 (msb) m p: rd oak: wr 357 h unchd 2-117 odt3 (lsb) m p: rd oak: wr 358 h unchd oak data reg. 3 2-117 odt3 (msb) m p: rd oak: wr 359 h unchd 2-117 odt4 (lsb) m p: rd oak: wr 35a h unchd oak data reg. 4 2-117 odt4 (msb) m p: rd oak: wr 35b h unchd 2-117 odt5 (lsb) m p: rd oak: wr 35c h unchd oak data reg. 5 2-117 odt5 (msb) m p: rd oak: wr 35d h unchd 2-117 table 5-22 clocks reg name access address reset value comment page no. ccsel0 rd/wr 360 h 0001 00xx (1) (1) bits [1:0] are read-only and depends on values of freq0, freq1 pins during reset 2-125 ccsel1 rd/wr 361 h 00 h clocks select reg. 1 2-126 table 5-21 oak mail box (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-18 1997-11-01 ccsel2 rd/wr 362 h 00 h clocks select reg. 2 2-128 testen rd/wr 363 h 00 h clocks select reg. 1 2-126 table 5-23 iom/pcm mux reg name access address reset value comment page no. mmode rd/wr 380 h 01 h mux mode bits[7:4] reserved 2-53 mc chsel0 rd/wr 381 h 00 h channel selection reg. 0 2-54 mc chsel1 rd/wr 382 h 00 h channel selection reg. 1 2-55 mc chsel2 rd/wr 383 h 00 h channel selection reg. 2 2-56 mp chsel0 rd/wr 384 h 00 h 2-57 table 5-24 uart reg name access address reset value comment page no. rbr rd 3a0 h lcr:dlab = 0 2-139 thr wr 3a0 h lcr:dlab = 0 2-139 ier rd/wr 3a1 h lcr:dlab = 0 2-151 iir rd 3a2 h 2-149 fcr wr 3a2 h 2-148 lcr rd/wr 3a3 h 2-143 mcr rd/wr 3a4 h 2-151 lsr rd 3a5 h written during production testing 2-145 msr rd/wr 3a6 h 2-153 table 5-22 clocks (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-19 1997-11-01 scr rd/wr 3a7 h 2-154 dll rd/wr 3a0 h div. lat. (ls); lcr: dlab = 1 2-140 dlm rd/wr 3a1 h div. lat. (ms); lcr:dlab = 1 2-140 table 5-25 pediu reg name access address reset value comment page no. ucr rd/wr c100 h 00 h pediu control register 2-93 usr rd c101 h pediu status register 2-97 uisbper set c102 h 00 h pediu input stream 2-101 reset c103 h bypass rd c104 h enable regiser uosbpr rd c105 h 00 h pediu output stream bypass enable regise 2-103 set c106 h reset c107 h utsr set c108 h 00 h pediu tri-state register 2-104 reset c109 h rd c10a h uprtar rd/wr c10b h pediu-rom test address register 2-106 uprtdr rd c10c h pediu-rom test data register 2-106 table 5-26 dcu reg name access address reset value comment page no. bootconf c001 h boot configuration register 2-79 memconfr c002 h 0007 h memory configuration register 2-68 testconfr c003 h test configuration register 2-69 statc c004 h unchd run time statistics counter 2-71 table 5-24 uart (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-20 1997-11-01 statr c005 h unchd run time statistics register 2-71 passr c006 h 0000 h program write protection register 2-73 jconf coo7 h 8000 h serial emulation configuration register. bit 14 is determined by strap 2-73 table 5-27 oak mail box reg name access address reset value comment page no. mcmd m p: wr oak: rd c040 h 0000 h microprocessor command 2-117 mbusy m p: wr oak: rd c041 h 0000 h microprocessor mail box busy 2-117 mdt0 m p: wr oak: rd c042 h unchd microprocessor data reg. 0 2-117 mdt1 m p: wr oak: rd c044 h unchd microprocessor data reg.1 2-117 mdt2 m p: wr oak: rd c046 h unchd microprocessor data reg. 2 2-117 mdt3 m p: wr oak: rd c048 h unchd microprocessor data reg. 3 2-117 mdt4 m p: wr oak: rd c04a h unchd microprocessor data reg. 4 2-117 mdt5 m p: wr oak: rd c04c h unchd microprocessor data reg. 5 2-117 ocmd m p: rd oak: wr c050 h 0000 h oak command 2-117 obusy m p: rd oak: wr c051 h 0000 h oak mail box busy 2-117 odt0 m p: rd oak: wr c052 h unchd oak data reg. 0 2-117 table 5-26 dcu (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-21 1997-11-01 odt1 m p: rd oak: wr c054 h unchd oak data reg.1 2-117 odt2 m p: rd oak: wr c056 h unchd oak data reg. 2 2-117 odt3 m p: rd oak: wr c058 h unchd oak data reg. 3 2-117 odt4 m p: rd oak: wr c05a h unchd oak data reg. 4 2-117 odt5 m p: rd oak: wr c05c h unchd oak data reg. 5 2-117 table 5-27 oak mail box (contd) reg name access address reset value comment page no. peb 20560 description of registers semiconductor group 5-22 1997-11-01 5.1.1 elic0 and elic1 registers description 5.1.1.1 interrupt top level 5.1.1.1.1 interrupt status register (ista) access: read reset value: 00 h iwd interrupt watchdog timer (elic0 only). the watchdog timer is expired and an external reset (resin) was generated. the software failed to program the bits wtc1 and wtc2 in wtc register in the correct sequence. ida interrupt d-channel arbiter. the suspend counter expired while the arbiter was in the state expect frame. the affected d-channel can be determined by reading register astate. iep interrupt epic-1, detailed information is indicated in register ista_e. exb extended interrupt sacco-b, detailed information is indicated in register exir_b. icb interrupt sacco-b, detailed information is indicated in register ista_b. exa extended interrupt sacco-a, detailed information is indicated in register exir_a. ica interrupt sacco-a, detailed information is indicated in register ista_a. iwd and ida are reset when reading ista. the other bits are reset when reading the corresponding local ista- or exir-register. bit 7 bit 0 iwd ida iep exb icb exa ica 0 peb 20560 description of registers semiconductor group 5-23 1997-11-01 5.1.1.1.2 mask register (mask) access: write reset value: 00 h (all interrupts enabled) ida enables(0)/disables(1) the d-channel arbiter interrupt iep enables(0)/disables(1) the epic-1 interrupts exb enables(0)/disables(1) the sacco-b extended interrupts icb enables(0)/disables(1) the sacco-b interrupts exa enables(0)/disables(1) the sacco-a extended interrupts ica enables(0)/disables(1) the sacco-a interrupts each interrupt source/group can be selectively masked by setting the respective bit in the mask-register (bit position corresponding to the ista-register). a masked ida- interrupt is not indicated when reading ista. instead it remains internally stored and will be indicated after the respective mask-bit is reset. the watchdog timer interrupts is not maskable. even with a set mask-bit epic-1 and sacco-interrupts are indicated but no interrupt signal is generated. when writing the mask-register while an interrupt is indicated, int is temporarily set into the inactive state. 5.1.1.2 watchdog timer (in elic0 only) 5.1.1.2.1 watchdog control register (wtc) access: read/write reset value: 1f h swt start watchdog timer. when set, the watchdog timer is started. the only way to disable it, is a elic-reset (power-up or dreset ). bit 7 bit 0 0 ida iep exb icb exa ica 0 bit 7 bit 0 wtc1 wtc2 swt 11111 peb 20560 description of registers semiconductor group 5-24 1997-11-01 wtc12 watchdog timer control. once the watchdog timer has been started wtc1, wtc2 have to be written once every 1024 pfs-cycles in the following sequence in order to prevent the watchdog expiring. wtc1 wtc2 1) 1 0 2) 0 1 the minimum required interval between the two write accesses is 2 pdc-periods. 5.1.1.3 elic ? mode register access: read/write reset value: xf h ecmd2 elic cfi-mode bit 2. if set to 0, the cfi-mode 0 with a 2.048-mbit/s data rate can be used with a 2.048-mhz pdc-input clock. this mode requires further restrictions of the current elic-specification: 1) epic-1 pmod:pcr must be set to 1. note: although the pcm clock pdc is set to double clock rate by this bit, the data rate must always be equal to the clock rate. 2) epic-1 cmd2:coc must be programmed to 0, i.e. it is not possible to output a dcl-clock with a frequency of twice the cfi-data rate. 3) epic-1 cmd1:css must be programmed to 0, i.e. it is not possible to select dcl as clock and fsc as framing signal source for the configurable interface. 4) the timing of the pcm-interface is expanded: bit 7 bit 0 dont care 1 1 ecmd2 1 table 5-28 parameter symbol limit values unit test condition min. max. clock period t cp 480 C ns emod:ecmd2 = 0 clock period low t cpl 200 C ns clock period high t cph 200 C ns peb 20560 description of registers semiconductor group 5-25 1997-11-01 5) pcsr:dre has to be set to 1. pcsr:ure has to be set to 1. when provided with a 2 mhz pdc, the elic internally generates a 4 mhz clock. since the clock shift capabilities (provided by register bits pcsr:drcs and pcsr:adsr0) apply to the internal 4 mhz clock, the frame can thus be shifted with a resolution of a half bit. figure 5-1 timing relation between internal and external clock 6) pmod:psm has to be set to 1. the frame signal pfs must always be sampled with the rising edge of pdc. the set-up and hold times of pfs are still valid respected to external pdc. its06897 epic r core x2 r elic 4 mhz pdc = 2 mhz rxd#, txd# (2 mbit/s) 2 mhz pdc internal 4 mhz clock peb 20560 description of registers semiconductor group 5-26 1997-11-01 5.1.1.4 epic ? -1 5.1.1.4.1 pcm-mode register (pmod) access: read/write reset value: 00 h note: if emod:ecmd2 is set to 0 some restrictions apply to the setting of register pmod (see chapter 5.1.1.3 ). pmd10 pcm-mode. defines the actual number of pcm-ports, the data rate range and the data rate stepping. the actual selection of physical pins is described below (ais1/0). pcr pcm-clock rate. 0single clock rate, data rate is identical with the clock frequency selected for elic pdc input. 1double clock rate, data rate is half the clock frequency selected for elic pdc input. note: only single clock rate is allowed in pcm-mode 2! psm pcm synchronization mode. a rising edge on pfs synchronizes the pcm-frame. pfs is not evaluated directly but is sampled with pdc. 0the external pfs is evaluated with the falling edge of pdc. the internal pfs (internal frame start) occurs with the next rising edge of pdc. 1the external pfs is evaluated with the rising edge of pdc. the internal pfs (internal frame start) occurs with this rising edge of pdc. bit 7 bit 0 pmd1 pmd0 pcr psm ais1 ais0 aic1 aic0 table 5-29 pmd10 pcm-mode port count data rate [mbit/s] data rate stepping [kbit/s] min. max. 00 01 10 11 0 1 2 3 4 2 1 2 256 512 1024 512 2048 4096 8192 4096 256 512 1024 512 peb 20560 description of registers semiconductor group 5-27 1997-11-01 ais10 alternative input selection (only in pcm-ports-mux mode 0 possible). these bits determine the relationship between the physical pins and the logical port numbers. the logical port numbers are used when programming the switching functions. note: in pcm-mode 0 these bits may not be set! aic1 alternate input comparison 1. 0input comparison of port 2 and 3 is disabled 1the inputs of port 2 and 3 are compared aic0 alternate input comparison 0. 0input comparison of port 0 and 1 is disabled 1the inputs of port 0 and 1 are compared note: the comparison function is operational in all pcm-modes; however, a redundant pcm-line which can be switched over to by means of the pmod: ais-bits is only available in pcm-modes 1, 2 and 3. table 5-30 pcm port 0 port 1 port 2 port 3 mode rxd0 txd0 tsc0 rxd1 txd1 tsc1 rxd2 txd2 tsc2 rxd3 txd3 tsc3 0 in0 out0 val0 in1 out1 val1 in2 out2 val2 in3 out3 val3 1 in0 (ais0 =1) out0 val0 in0 (ais0 =0) tri- state ais0 in1 (ais1 =1) out1 val1 in1 (ais1 =0) tri- state ais1 2 not active out val not active tri- state ais0 in (ais1 =1) undef. undef. in (ais1 =0) tri- state ais1 3 in0 (ais0 =1) out0 val0 in0 (ais0 =0) out0 val0 in1 (ais1 =1) out1 val1 in1 (ais1 =0) out1 val1 peb 20560 description of registers semiconductor group 5-28 1997-11-01 5.1.1.4.2 bit number per pcm-frame (pbnr) access: read/write reset value: ff h bnf70 bit number per pcm frame. pcm-mode 0: bnf70 = number of bits C 1 pcm-mode 1: bnf70 = (number of bits C 2) / 2 pcm-mode 2: bnf70 = (number of bits C 4) / 4 pcm-mode 3: bnf70 = (number of bits C 2) / 2 the value programmed in pbnr is also used to check the pfs-period. 5.1.1.4.3 pcm-offset downstream register (pofd) access: read/write reset value: 00 h ofd92 offset downstream bit 92. these bits together with pcsr:ofd10 determine the offset of the pcm-frame in downstream direction. the following formulas apply for calculating the required register value. bnd is the bit number in downstream direction marked by the rising internal pfs-edge. bpf denotes the actual number of bits constituting a frame. pcm-mode 0: ofd92 = mod bpf (bnd C 17 + bpf) pcsr:ofd1..0 = 0 pcm-mode 1,3: pfd91 = mod bpf (bnd - 33 + bpf) pcsr: pfd0 = 0 pcm-mode 2: ofd90 = mod bpf (bnd - 65 + bpf) bit 7 bit 0 bnf7 bnf6 bnf5 bnf4 bnf3 bnf2 bnf1 bnf0 bit 7 bit 0 ofd9 ofd8 ofd7 ofd6 ofd5 ofd4 ofd3 ofd2 peb 20560 description of registers semiconductor group 5-29 1997-11-01 5.1.1.4.4 pcm-offset upstream register (pofu) access: read/write reset value: 00 h ofu92 offset upstream bit 92. these bits together with pcsr:ofu10 determine the offset of the pcm-frame in upstream direction. the following formulas apply for calculating the required register value. bnu is the bit number in upstream direction marked by the rising internal pfs-edge. pcm-mode 0: ofu92 = mode bpf (bnu + 23) pcsr:ofu100 = 0 pcm-mode 1, 3: ofu91 = mod bpf (bnu + 47) pcsr:ofu0 = 0 pcm-mode 2: ofu90 = mod bpf (bnu + 95) 5.1.1.4.5 pcm-clock shift register; within the elic (pcsr) access: read/write reset value: 00 h drcs double rate clock shift. 0the pcm-input and output data are not delayed 1the pcm-input and output data are delayed by one pdc-clock cycle ofd10 offset downstream bits 10, see pofd-register. dre downstream rising edge. 0the pcm-data is sampled with the falling edge of pdc 1the pcm-data is sampled with the rising edge of pdc adsro add shift register on output. 0the pcm-output data are not delayed 1the pcm-output data are delayed by one pdc-clock cycle note: if both drcs and adsro are set to logical 1, the pcm-output data are delayed by two pdc-clock cycles. ofu10 offset upstream bits 10, see pofu-register . bit 7 bit 0 ofu9 ofu8 ofu7 ofu6 ofu5 ofu4 ofu3 ofu2 bit 7 bit 0 drcs ofd1 ofd0 dre adsro ofu1 ofu0 ure peb 20560 description of registers semiconductor group 5-30 1997-11-01 ure upstream rising edge. 0the pcm-data is transmitted with the falling edge of pdc 1the pcm-data is transmitted with the rising edge of pdc note: if emod:ecmd2 is set to 0 some restrictions apply to the setting of pcsr (see chapter 5.1.1.3) . 5.1.1.4.6 pcm-input comparison mismatch (picm) access: read/write reset value: xx h ipn input pair number. this bit denotes the pair of ports, where a bit mismatch occurred. 0mismatch between ports 0 and 1 1mismatch between ports 2 and 3 tsn60 time-slot number. when a bit mismatch occurred these bits identify the affected bit position. 5.1.1.4.7 configurable interface mode register 1 (cmd1) access: read/write reset value: 00 h css clock source selection. 0pdc and pfs are used as clock and framing source for the cfi. clock bit 7 bit 0 ipn tsn6 tsn5 tsn4 tsn3 tsn2 tsn1 tsn0 table 5-31 pcm-mode time-slot identification bit identification 0 tsn6tsn2 + 2 tsn1, 0: 00 bits 6,7 01 bits 4,5 10 bits 2,3 11 bits 0,1 1, 3 tsn6tsn1 + 4 tsn0: 0 bits 47 1 bits 03 2 tsn6tsn0 + 8 bit 7 bit 0 css csm csp1 csp0 cmd1 cmd0 cis1 cis0 peb 20560 description of registers semiconductor group 5-31 1997-11-01 and framing signals derived from these sources are output on dcl and fsc. 1dcl and fsc are selected as clock and framing source for the cfi. if emod:ecmd2 is set to 0, then css has to be set to 0 (see chapter 5.1.1.3 ). note: both elics must be programmed in the same way. csm cfi-synchronization mode. the rising fsc-edge synchronizes the cfi-frame. 0fsc is evaluated with every falling edge of dcl. 1fsc is evaluated with every rising edge of dcl. note: if css = 0 is selected, csm and pmod:psm must be programmed identical. csp10 clock source prescaler 1,0. the clock source frequency is divided according to the following table to obtain the cfi-reference clock crcl. cmd10 cfi-mode1,0. defines the actual number and configuration of the cfi-ports. table 5-32 csp1,0 prescaler divisor 00 2 01 1.5 10 1 11 not allowed table 5-33 cmd 10 cfi- mode number of logical ports cfi-data rate [mbit/s] min. required cfi-data rate [kbit/s] relative to pcm-data rate necessary reference clock (rcl) dcl-output frequencies cmd1: css0 = 0 min. max. 00 0 4 du (03) 128 2048 32n/3 2xdr dr, 2xdr 1) 01 1 2 du (01) 128 4096 64n/3 dr dr peb 20560 description of registers semiconductor group 5-32 1997-11-01 where n = number of time-slots in a pcm-frame cis10 cfi alternative input selection. in cfi-mode 1 and 2 cis10 controls the assignment between logical and physical receive pins. in cfi-mode 0 and 3 cis1,0 should be set to 0. 10 2 1 du 128 8192 64n/3 0.5xdr dr 11 3 8 bit (07) 128 1024 16n/3 4xdr dr, 2xdr 1) in cfi-mode 0 data rate of 2.048 mbit/s can be used with a 2.048-mbit/s pdc-input clock, if emod:ecmd2 = 0. refer to chapter 5.1.1.3 elic-mode register (emod) . table 5-34 cfi- mode port 0 port 1 port 2 port 3 du0 dd0 du1 dd1 du2 dd2 du3 dd3 0 in0 out0 in1 out1 in2 out2 in3 out3 1 in0 cis0 = 0 out0 in1 cis1 = 0 out1 in0 cis0 = 1 tri- state in1 cis1 = 1 tri- state 2 in cis0 = 0 out not active tri- state in cis0 = 1 tri- state not active tri- state 3 this mode is not allowed in the doc.. table 5-33 (contd) cmd 10 cfi- mode number of logical ports cfi-data rate [mbit/s] min. required cfi-data rate [kbit/s] relative to pcm-data rate necessary reference clock (rcl) dcl-output frequencies cmd1: css0 = 0 min. max. peb 20560 description of registers semiconductor group 5-33 1997-11-01 5.1.1.4.8 configurable interface mode register 2 (cmd2) access: read/write reset value: 00 h fc20 framing output control. given that cmd1:css = 0, these bits determine the position of the fsc-pulse relative to the cfi-frame, as well as the type of fsc-pulse generated. the position and width of the fsc-signal with respect to the cfi-frame can be found in the following two figure 5-2 and figure 5-3 . figure 5-2 position of the fsc-signal for fc-modes 3 and 6 figure 5-3 position of the fsc-signal for fc-mode 6 bit 7 bit 0 fc2 fc1 fc0 coc 0 0 cbn9 cbn8 itd05851 last time-slot of a frame time-slot 0 cfi rcl dcl dcl dcl fsc fsc conditions: cfi mode 0; cmd2 : coc = 1 cfi modes 1, 2; cmd2 : coc = 0 cmd2 : fc2...0 = 011 (fc mode 3) frame cfi mode 0; cmd2 : coc = 0 cfi mode 3; cmd2 : coc = 1 cfi mode 3; coc = 0 cmd2 : fc2...0 = 010 (fc mode 6) itd05852 012345 frame fsc rcl cfi cmd2 : fc2...0 = 110 (fc mode 6) conditions: time-slot peb 20560 description of registers semiconductor group 5-34 1997-11-01 application examples: for further details on the framing output control please refer to chapter 5.1.1.4.8 . coc cfi-output clock rate. 0the frequency of dcl is identical to the cfi-data rate (all cfi-modes), 1the frequency of dcl is twice the cfi-data rate (cfi-modes 0 and 3 only!) note: 1) applies only if cmd1:css = 0. if emod:ecmd2 is set to 0 then cmd2:coc must be set to 0 (see chapter 5.1.1.3 ). 2) crr must be set to 0 in cfi-mode 3. cbn98 cfi-bit number 98 these bits, together with the cbnr:cbn70, hold the number of bits per cfi-frame. 5.1.1.4.9 configurable interface bit number register (cbnr) access: read/write reset value: ff h cbn70 cfi-bit number 70. the number of bits that constitute a cfi-frame must be programmed to cmd2, cbnr:cbn90 as indicated below. cbn90 = number of bits - 1 for a 8-khz frame structure, the number of bits per frame can be derived from the data rate by division with 8000. table 5-35 fc2 fc1 fc0 fc-mode main applications 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 not allowed not allowed not allowed general purpose not allowed reserved iom-2 software timed multiplexed applications bit 7 bit 0 cbn7 cbn6 cbn5 cbn4 cbn3 cbn2 cbn1 cbn0 peb 20560 description of registers semiconductor group 5-35 1997-11-01 5.1.1.4.10 configurable interface time-slot adjustment register (ctar) access: read/write reset value: 00 h tsn60 time-slot number. the cfi-framing signal (pfs if cmd1:css = 0 or fsc if cmd1:css = 1) marks the cfi time-slot called tsn according to the following formula: tsn60 = tsn + 2 e.g.: if the framing signal is to mark time-slot 0 (bit 7), ctar must be set to 02 h (cbsr to 20 h ). note: if cmd1:css = 0, the cfi-frame will be shifted - together with the fsc-output signal - with respect to pfs. the position of the cfi-frame relative to the fsc-output signal is not affected by these settings, but is instead determined by cmd2:fc2 .. 0. if cmd1:css = 1, the cfi-frame will be shifted with respect to the fsc-input signal. 5.1.1.4.11 configurable interface bit shift register (cbsr) access: read/write reset value: 00 h sfsc shift fsc 0default (behaviour like epic-1 peb 2055) 1with double clock rate the fsc input is delayed by one and a half cfi clock cycle (iom-2 compatibility) bit 7 bit 0 0 tsn6 tsn5 tsn4 tsn3 tsn2 tsn1 tsn0 bit 7 bit 0 sfsc cds2 cds1 cds0 cus3 cus2 cus1 cus0 peb 20560 description of registers semiconductor group 5-36 1997-11-01 figure 5-4 internal fsc shift to enable a synchronization with the rising edge of dcl itt10075 internal fsc cbsr:sfsc external fsc dcl du dd mco 1st bit dcl fsc dd du (elic r ) r (elic ) dd du -2 spec iom r requirement 1st bit 1st bit delayed fsc case:sfsc = 1 last bit 1st bit 1st bit last bit 1st bit last bit 1st bit internal frame start dd du shifted 1st bit to the left internal frame start if cbsr:sfsc = 0 peb 20560 description of registers semiconductor group 5-37 1997-11-01 cds20 cfi-downstream bit shift 20. from the zero offset bit position (cbsr = 20 h ) the cfi-frame (downstream and upstream) can be shifted by up to 6 bits to the left (within the time-slot number tsn programmed in ctar) and by up to 2 bits to the right (within the previous time-slot tsn C 1) by programming the cbsr:cds20 bits: the bit shift programmed to cbsr:cds20 affects both the upstream and downstream frame position in the same way. cus32 cfi-upstream bit shift 30. these bits shift the upstream cfi-frame relative to the downstream frame by up to 15 bits. for cus30 = 0000, the upstream frame is aligned with the downstream frame (no bit shift). 5.1.1.4.12 configurable interface subchannel register (cscr) access: read/write reset value: 00 h sc#1#0 cfi-subchannel control for logical port #. the subchannel control bits sc#1sc#0 specify separately for each logical port the bit positions to be exchanged with the data memory (dm) when a connection with a channel bandwidth as defined by the cm-code has been established: table 5-36 cbsr:cds20 time-slot no. bit no. 000 001 010 011 100 101 110 111 tsn C 1 tsn C 1 tsn tsn tsn tsn tsn tsn 1 0 7 6 5 4 3 2 bit 7 bit 0 sc31 sc30 sc21 sc20 sc11 sc10 sc01 sc00 peb 20560 description of registers semiconductor group 5-38 1997-11-01 note: in cfi-mode 1: sc21 = sc01; sc20 = sc00; sc31 = sc11; sc30 = sc10 in cfi-mode 2: sc31 = sc21 = sc11 = sc01; sc30 = sc20 = sc10 = sc00 5.1.1.4.13 memory access control register (macr) access: read/write reset value: xx h with the macr the m p selects the type of memory (cm or dm), the type of field (data or code) and the access mode (read or write) of the register access. when writing to the control memory code field, macr also contain the 4 bit code (cmc3..0) defining the function of the addressed cfi time-slot. rws read/write select. 0write operation on control or data memories 1read operation on control or data memories moc30 memory operation code. cmc30 control memory code. these bits determine the type and destination of the memory operation as shown below. note: prior to a new access to any memory location (i.e. writing to macr) the star:mac bit must be polled for 0. table 5-37 sc#1 sc#0 bit positions for cfi subchannels having a bandwidth of 64 kbit/s 32 kbit/s 16 kbit/s 0 0 1 1 0 1 0 1 70 70 70 70 74 30 74 30 76 54 32 10 bit 7 bit 0 rws moc3 moc2 moc1 moc0 cmc3 cmc2 cmc1 cmc0 peb 20560 description of registers semiconductor group 5-39 1997-11-01 1. writing data to the upstream dm-data field (e.g. pcm-idle code). reading data from the upstream or downstream dm-data field. moc30 defines the bandwidth and the position of the subchannel as shown below: note: when reading a dm-data field location, all 8 bits are read regardless of the bandwidth selected by the moc-bits. 2. writing to the upstream dm-code (tri-state) field. control-reading the upstream dm-code (tri-state). moc = 1100 read/write tri-state info from/to single pcm time-slot moc = 1101 write tri-state info to all pcm time-slots note: the tri-state field is exchanged with the 4 least significant bits (lsbs) of the madr. 3. writing data to the upstream or downstream cm-data field (e.g. signaling code). reading data from the upstream or downstream cm-data field. macr: rws moc3 moc2 moc1 moc0 0 0 0 table 5-38 moc30 transferred bits channel bandwidth 0000 0001 0011 0010 0111 0110 0101 0100 C bits 70 bits 74 bits 30 bits 76 bits 54 bits 32 bits 10 C 64 kbit/s 32 kbit/s 32 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s macr: rws moc3 moc2 moc1 moc0 0 0 0 macr: rws1001000 peb 20560 description of registers semiconductor group 5-40 1997-11-01 4. writing data to the upstream or downstream cm-data field and code field (e.g. switching a cfi to/from pcm-connection). the 4-bit code field of the control memory (cm) defines the functionality of a cfi time-slot and thus the meaning of the corresponding data field. this 4-bit code, written to the macr:cmc30 bit positions, will be transferred to the cm-code field. the 8-bit madr value is at the same time transferred to the cm-data field. there are codes for switching applications, pre-processed applications and for direct m p-access applications, as shown below: a) switching applications cmc = 0000 unassigned channel (e.g. cancelling an assigned channel) cmc = 0001 bandwidth 64 kbit/s pcm time-slot bits transferred: 70 cmc = 0010 bandwidth 32 kbit/s pcm time-slot bits transferred: 30 cmc = 0011 bandwidth 32 kbit/s pcm time-slot bits transferred: 74 cmc = 0100 bandwidth 16 kbit/s pcm time-slot bits transferred: 10 cmc = 0101 bandwidth 16 kbit/s pcm time-slot bits transferred: 32 cmc = 0110 bandwidth 16 kbit/s pcm time-slot bits transferred: 54 cmc = 0111 bandwidth 16 kbit/s pcm time-slot bits transferred: 76 note: the corresponding cfi time-slot bits to be transferred are chosen in the cscr-register. b) pre-processed applications macr: 0111 cmc3 cmc2 cmc1 cmc0 table 5-39 downstream application even cm address odd cm address decentral d-channel handling cmc = 1000 cmc = 1011 central d-channel handling cmc = 1010 cmc = pcm-code for a 2-bit subtime-slot 6-bit signaling (e.g. analog iom) cmc = 1010 cmc = 1011 8-bit signaling (e.g. sld) cmc = 1010 cmc = 1011 d-channel handling by sacco-a with elic-arbiter cmc = 1010 cmc = 1011 peb 20560 description of registers semiconductor group 5-41 1997-11-01 c) m p-access applications setting cmc = 1001, initializes the corresponding cfi time-slot to be accessed by the m p. concurrently, the datum in madr is written (as 8-bit cfi-idle code) to the cm-data field. the content of the cm-data field is directly exchanged with the corresponding time-slot. note: that once the cm-code field has been initialized, the cm-data field can be written and read as described in chapter 3 . 5. control-reading the upstream or downstream cm-code. the cm-code can then be read out of the 4 lsbs of the madr-register. table 5-40 upstream application even cm address odd cm address decentral d-channel handling cmc = 1000 cmc = 0000 central d-channel handling cmc = 1000 cmc = pcm-code for a 2-bit subtime-slot 6-bit signaling (e.g. analog iom) cmc = 1010 cmc = 1010 8-bit signaling (e.g. sld) cmc = 1011 cmc = 1011 all code combinations are also valid for elic-arbiter operation. macr: 01111001 macr: 11110000 peb 20560 description of registers semiconductor group 5-42 1997-11-01 5.1.1.4.14 memory access address register (maar) access: read/write reset value: xx h the memory access address register maar specifies the address of the memory access. this address encodes a cfi time-slot for control memory (cm) and a pcm time-slot for data memory (dm) accesses. bit 7 of maar (u/d -bit) selects between upstream and downstream memory blocks. bits ma60 encode the cfi- or pcm-port and time-slot number as in the following tables: bit 7 bit 0 u/d ma6 ma5 ma4 ma3 ma2 ma1 ma0 table 5-41 time-slot encoding for data memory accesses data memory address pcm-mode 0 bit u/d bits ma6ma3, ma0 bits ma2ma1 direction selection time-slot selection logical pcm-port number pcm-mode 1,3 bit u/d bits ma6ma3, ma1, ma0 bit ma2 direction selection time-slot selection logical pcm-port number pcm-mode 2 bit u/d bits ma6ma0 direction selection time-slot selection table 5-42 time-slot encoding for control memory accesses control memory address cfi-mode 0 bit u/d bits ma6ma3, ma0 bits ma2ma1 direction selection time-slot selection logical cfi-port number cfi-mode 1 bit u/d bits ma6ma3, ma2, ma0 bit ma1 direction selection time-slot selection logical cfi-port number cfi-mode 2 bit u/d bits ma6ma0 direction selection time-slot selection cfi-mode 3 bit u/d bits ma6ma4, ma0 bits ma3ma1 direction selection time-slot selection logical cfi-port number peb 20560 description of registers semiconductor group 5-43 1997-11-01 5.1.1.4.15 memory access data register (madr) access: read/write reset value: xx h the memory access data register madr contains the data to be transferred from or to a memory location. the meaning and the structure of this data depends on the kind of memory being accessed. 5.1.1.4.16 synchronous transfer data register (stda) access: read/write reset value: xx h the stda-register buffers the data transferred over the synchronous transfer channel a. mtda7 to mtda0 hold the bits 7 to 0 of the respective time-slot. mtda7 (msb) is the bit transmitted/received first, mtda0 (lsb) the bit transmitted/received last over the serial interface. 5.1.1.4.17 synchronous transfer data register b (stdb) access: read/write reset value: xx h the stda-register buffers the data transferred over the synchronous transfer channel a. mtda7 to mtda0 hold the bits 7 to 0 of the respective time-slot. mtda7 (msb) is the bit transmitted/received first, mtda0 (lsb) the bit transmitted/received last over the serial interface. bit 7 bit 0 md7 md6 md5 md4 md3 md2 md1 md0 bit 7 bit 0 mtda7 mtda6 mtda5 mtda4 mtda3 mtda2 mtda1 mtda0 bit 7 bit 0 mtdb7 mtdb6 mtdb5 mtdb4 mtdb3 mtdb2 mtdb1 mtdb0 peb 20560 description of registers semiconductor group 5-44 1997-11-01 5.1.1.4.18 synchronous transfer receive address register a (sara) access: read/write reset value: xx h the sara-register specifies for synchronous transfer channel a from which input interface, port and time-slot the serial data is extracted. this data can then be read from the stda-register. isra interface select receive for channel a. 0selects the pcm-interface as the input interface for synchronous channel a. 1selects the cfi-interface as the input interface for synchronous channel a. mtra60 m p-transfer receive address for channel a; selects the port and time-slot number at the interface selected by isra according to table 2-7 and table 2-8 : mtra60 = ma60. 5.1.1.4.19 synchronous transfer receive address register b (sarb) access: read/write reset value: xx h the sarb-register specifies for synchronous transfer channel b from which input interface, port and time-slot the serial data is extracted. this data can then be read from the stdb register. isrb interface select receive for channel b. 0selects the pcm-interface as the input interface for synchronous channel b. 1selects the cfi-interface as the input interface for synchronous channel b. mtrb60 m p-transfer receive address for channel b; selects the port and time-slot number at the interface selected by isrb according to table 2-7 and table 2-8 : mtrb60 = ma60. bit 7 bit 0 isra mtra6 mtra5 mtra4 mtra3 mtra2 mtra1 mtra0 bit 7 bit 0 isrb mtrb6 mtrb5 mtrb4 mtrb3 mtrb2 mtrb1 mtrb0 peb 20560 description of registers semiconductor group 5-45 1997-11-01 5.1.1.4.20 synchronous transfer transmit address register a (saxa) access: read/write reset value: xx h the saxa-register specifies for synchronous transfer channel a to which output interface, port and time-slot the serial data contained in the stda-register is sent. isxa interface select transmit for channel a. 0selects the pcm-interface as the output interface for synchronous channel a. 1selects the cfi-interface as the output interface for synchronous channel a. mtxa6 0 m p-transfer transmit address for channel a; selects the port and time-slot number at the interface selected by isxa according to table 2-7 and table 2-8 : mtxa60 = ma60. 5.1.1.4.21 synchronous transfer transmit address register b (saxb) access: read/write reset value: xx h the saxb-register specifies for synchronous transfer channel b to which output interface, port and time-slot the serial data contained in the stdb-register is sent. isxb interface select transmit for channel b. 0selects the pcm-interface as the output interface for synchronous channel b. 1selects the cfi-interface as the output interface for synchronous channel b. mtxb60 m p-transfer transmit address for channel b; selects the port and time-slot number at the interface selected by isxb according to table 2-7 and table 2-8 : mtxb60 = ma60. bit 7 bit 0 isxa mtxa6 mtxa5 mtxa4 mtxa3 mtxa2 mtxa1 mtxa0 bit 7 bit 0 isxb mtxb6 mtxb5 mtxb4 mtxb3 mtxb2 mtxb1 mtxb0 peb 20560 description of registers semiconductor group 5-46 1997-11-01 5.1.1.4.22 synchronous transfer control register (stcr) access: read/write reset value: 00xxxxxx b the stcr-register bits are used to enable or disable the synchronous transfer utility and to determine the subtime slot bandwidth and position if a pcm-interface time-slot is involved. tae, tbe transfer channel a (b) enable. 1enables the m p transfer of the corresponding channel. 0disables the m p transfer of the corresponding channel. cta20 channel type a (b); these bits determine the bandwidth of the channel and the position of the relevant bits in the time-slot according to the table below. ctb20 note that if a cfi time-slot is selected as receive or transmit time-slot of the synchronous transfer, the 64-kbit/s bandwidth must be selected (ct#2ct#0 = 001). bit 7 bit 0 tbe tae ctb2 ctb1 ctb0 cta2 cta1 cta0 table 5-43 ct#2 ct#1 ct#0 bandwidth transferred bits 000 001 010 011 100 101 110 111 not allowed 64 kbit/s 32 kbit/s 32 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s C bits 70 bits 30 bits 74 bits 10 bits 32 bits 56 peb 20560 description of registers semiconductor group 5-47 1997-11-01 5.1.1.4.23 mf-channel active indication register (mfair) access: read/write reset value: 00 h this register is only used in iom-2 applications (active handshake protocol) in order to identify active monitor channels when the search for active monitor channels command (cmdr:mfso) has been executed. so mf channel search on. 0the search is completed. 1the epic-1 is still busy looking for an active channel. sad50 subscriber address 50; after an ista:mac-interrupt these bits point to the port and time-slot where an active channel has been found. the coding is identical to mfsar:sad5sad0. 5.1.1.4.24 mf-channel subscriber address register (mfsar) access: read/write reset value: xx h the exchange of monitor data normally takes place with only one subscriber circuit at a time. this register serves to point the mf-handler to that particular cfi time-slot. mftc10 mf channel transfer control 10; these bits, in addition to cmdr:mft1,0 and omdr:mfps control the mf-channel transfer as indicated in table 5-44 . sad50 subscriber address 5..0; these bits define the addressed subscriber. the cfi time-slot encoding is similar to the one used for control memory accesses using the maar-register ( table 5-41 and table 5-42 ): cfi time-slot encoding of mfsar derived from maar: bit 7 bit 0 0 so sad5 sad4 sad3 sad2 sad1 sad0 bit 7 bit 0 mftc1 mftc0 sad5 sad4 sad3 sad2 sad1 sad0 maar: ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 mfsar: mftc1 mftc0 sad5 sad4 sad3 sad2 sad1 sad0 peb 20560 description of registers semiconductor group 5-48 1997-11-01 maar:ma7 selects between upstream and downstream cm-blocks. this information is not required since the transfer direction is defined by cmdr (transmit or receive). maar:ma0 selects between even and odd time-slots. this information is also not required since mf-channels are always located on even time-slots. 5.1.1.4.25 monitor/feature control channel fifo (mffifo) access: read/write reset value: empty the 16-byte bi-directional mffifo provides intermediate storage for data bytes to be transmitted or received over the monitor or feature control channel. mfd70 mf data bits 70; mfd7 (msb) is the first bit to be sent over the serial cfi, mfd0 (lsb) the last. note: the byte n + 1 of an n-byte transmit message in monitor channel is not defined. 5.1.1.4.26 signaling fifo (cififo) access: read reset value: 0xxxxxxx b the 9 byte deep cififo stores the addresses of cfi time-slots in which a c/i- and/or a sig-value change has taken place. this address information can then be used to read the actual c/i- or sig-value from the control memory. sbv signaling byte valid. 0the sad6..0 bits are invalid. 1the sad6..0 bits indicate a valid subscriber address. the polarity of sbv is chosen such that the whole 8 bits of the cififo can be copied to the maar register in order to read the upstream c/i- or sig-value from the control memory. sad60 subscriber address bits 60; the cm-address which corresponds to the cfi time-slot where a c/i- or sig-value change has taken place is encoded in these bits. for c/i-channels sad60 point to an even cm-address (c/i-value), for sig-channels sad60 point to an odd cm-address (stable sig-value). bit 7 bit 0 mfd7 mfd6 mfd5 mfd4 mfd3 mfd2 mfd1 mfd0 bit 7 bit 0 sbv sad6 sad5 sad4 sad3 sad2 sad1 sad0 peb 20560 description of registers semiconductor group 5-49 1997-11-01 5.1.1.4.27 timer register (timr) access: write reset value: 00 h the epic-1 timer can be used for 3 different purposes: timer interrupt generation (ista:tig), fsc multiframe generation (cmd2:fc20 = 111) and last look period generation. ssr signaling sampling rate. 0the last look period is defined by tval60. 1the last look period is fixed to 125 m s. tval60 timer value bits 60; the timer period, equal to (1 + tval60) 250 m s, is programmed here. it can thus be adjusted within the range of 250 m s up to 32 ms. the timer is started as soon as cmdr:st is set to 1 and stopped by writing the timr-register or by selecting omdr:oms0 = 0. 5.1.1.4.28 status register epic ? -1 (star_e) access: read reset value: 05 h the status register star displays the current state of certain events within the epic-1. the star register bits do not generate interrupts and are not modified by reading star. mac memory access 0no memory access is in operation. 1a memory access is in operation. hence, the memory access registers may not be used. note: mac is also set and reset during synchronous transfers. tac timer active 0the timer is stopped. 1the timer is running. pss pcm-synchronization status. 1the pcm-interface is synchronized. bit 7 bit 0 ssr tval6 tval5 tval4 tval3 tval2 tval2 tval0 bit 7 bit 0 mac tac pss mfto mfab mfae mfrw mffe peb 20560 description of registers semiconductor group 5-50 1997-11-01 0the pcm-interface is not synchronized. there is a mismatch between the pbnr-value and the applied clock and framing signals (pdc/pfs) or omdr:oms0 = 0. mfto mf-channel transfer in operation. 0no mf-channel transfer is in operation. 1an mf-channel transfer is in operation. mfab mf-channel transfer aborted. 0the remote receiver did not abort a handshake message transfer. 1the remote receiver aborted a handshake message transfer. mfae mffifo-access enable. 0the mffifo may not be accessed. 1the mffifo may be either read or written to. mfrw mffifo read/write. 0the mffifo is ready to be written to. 1the mffifo may be read. mffe mffifo empty 0the mffifo is not empty. 1the mffifo is empty. 5.1.1.4.29 command register epic ? -1 (cmdr_e) access: write reset value: 00 h writing a logical 1 to a cmdr-register bit starts the respective operation. st start timer. 0not action. if the timer shall be stopped, the timr-register must simply be written with a random value. 1starts the timer to run cyclically from 0 to the value programmed in timr:tval60. tig timer interrupt generation. 0setting the tig-bit to logical 0 together with the cmdr:st-bit set to logical 1 disables the interrupt generation. 1setting the tig-bit to logical 1 together with cmdr:st-bit set to logical1 causes the epic-1 to generate a periodic interrupt (ista:tin) each time the timer expires. bit 7 bit 0 0 st tig cfr mft1 mft0 mfso mffr peb 20560 description of registers semiconductor group 5-51 1997-11-01 cfr cififo reset. 0no action. 1resets the signaling fifo within 2 rcl-periods, i.e. all entries and the ista:sfi-bit are cleared. mft10 mf-channel transfer control bits 1,0; these bits start the monitor transfer enabling the contents of the mffifo to be exchanged with the subscriber circuits as specified in mfsar. the function of some commands depends furthermore on the selected protocol (omdr:mfps). table 5-44 summarizes all available mf-commands. mfso mf-channel search on. 0no action. 1the epic-1 starts to search for active mf-channels. active channels are characterized by an active mx-bit (logical 0) sent by the remote transmitter. if such a channel is found, the corresponding address is stored in mfair and an ista:mac-interrupt is generated. the search is stopped when an active mf-channel has been found or when omdr:oms0 is set to 0. mffr mffifo reset. 0no action 1resets the mffifo and all operations associated with the mf-handler (except for the search function) within 2 rcl-periods. the mffifo is set into the state mffifo empty, write access enabled and any monitor data transfer currently in process will be aborted. table 5-44 summary of mf-channel commands transfer mode cmdr: mft1,mft0 mfsar protocol selection application inactive 00 xxxxxxxx hs, no hs idle state transmit 01 00 sad50 hs, no hs iom-2, iom-1, sld transmit broadcast 01 01xxxxxx hs, no hs iom-2, iom-1, sld test operation 01 10------ hs, no hs iom-2, iom-1, sld transmit continuous 11 00 sad50 hs iom-2 peb 20560 description of registers semiconductor group 5-52 1997-11-01 hs: handshake facility enabled (omdr:mfps = 1) no hs: handshake facility disable (omdr:mfps = 0) 5.1.1.4.30 interrupt status register epic ? -1 (ista_e) access: read reset value: 00 h the ista-register should be read after an interrupt in order to determine the interrupt source. tin timer interrupt; a timer interrupt previously requested with cmdr:st, tig = 1 has occurred. the tin-bit is reset by reading ista. it should be noted that the interrupt generation is periodic, i.e. unless stopped by writing to timr, the ista:tin will be generated each time the timer expires. sfi signaling fifo-interrupt; this interrupt is generated if there is at least one valid entry in the cififo indicating a change in a c/i- or sig-channel. reading ista does not clear the sfi-bit. instead sfi is cleared if the cififo is empty which can be accomplished by reading all valid entries of the cififo or by resetting the cififo by setting cmdr:cfr to 1. transmit + receive same time-slot any # of bytes 1 byte expected 2 bytes expected 8 bytes expected 16 bytes expected 10 10 10 10 10 00 sad50 00 sad50 01 sad50 10 sad50 11 sad50 hs no hs no hs no hs no hs iom-2 iom-1 (iom-1) (iom-1) (iom-1) transmit + receive same line 1 byte expected 2 bytes expected 8 bytes expected 16 bytes expected 11 11 11 11 00 sad50 01 sad50 10 sad50 11 sad50 no hs no hs no hs no hs sld sld sld sld bit 7 bit 0 tin sfi mffi mac pfi pim sin sov table 5-44 summary of mf-channel commands (contd) transfer mode cmdr: mft1,mft0 mfsar protocol selection application peb 20560 description of registers semiconductor group 5-53 1997-11-01 mffi mffifo-interrupt; the last mf-channel command (issued by cmdr:mft1, mft0) has been executed and the epic-1 is ready to accept the next command. additional information can be read from star:mftomffe. mffi is reset by reading ista. mac monitor channel active interrupt; the epic-1 has found an active monitor channel. a new search can be started by reissuing the cmdr:mfso- command. mac is reset by reading ista. pfi pcm-framing interrupt; the star:pss-bit has changed its polarity. to determine whether the pcm-interface is synchronized or not, star must be read. the pfi-bit is reset by reading ista. pim pcm-input mismatch; this interrupt is generated immediately after the comparison logic has detected a mismatch between a pair of pcm-input lines. the exact reason for the interrupt can be determined by reading the picm-register. reading ista clears the pim-bit. a new pim-interrupt can only be generated after the picm-register has been read. sin synchronous transfer interrupt; the sin-interrupt is enabled if at least one synchronous transfer channel (a and/or b) is enabled via the stcr:tae, tbe-bits. the sin-interrupt is generated when the access window for the m p opens. after the occurrence of the sin-interrupt the m p can read and/or write the synchronous transfer data registers (stda, stdb). the sin-bit is reset by reading ista. sov synchronous transfer overflow; the sov-interrupt is generated if the m p fails to access the data registers (stda, stdb) within the access window. the sov-bit is reset by reading ista. 5.1.1.4.31 mask register epic ? -1 (mask_e) access: write reset value: 00 h a logical 1 disables the corresponding interrupt as described in the ista-register. a masked interrupt is stored internally and reported in ista immediately if the mask is released. however, an sfi-interrupt is also reported in ista if masked. in this case no interrupt is generated. when writing register mask_e while ista_e indicates a non masked interrupt int is temporarily set into the inactive state. bit 7 bit 0 tin sfi mffi mac pfi pim sin sov peb 20560 description of registers semiconductor group 5-54 1997-11-01 5.1.1.4.32 operation mode register (omdr) access: read/write reset value: 00 h oms101 operational mode selection; these bits determine the operation mode of the epic-1 is working in according to the following table: bit 7 bit 0 oms1 oms0 psb ptl 0 or 1 mfps csb rbs table 5-45 oms10 function 00 the cm-reset mode is used to reset all locations of the control memory code and data fields with a single command within only 256 rcl-cycles. a typical application is resetting the cm with the command macr = 70 h which writes the contents of madr (xx h ) to all data field locations and the code 0000 (unassigned channel) to all code field locations. a cm-reset should be made after each hardware reset. in the cm-reset mode the epic-1 does not operate normally i.e. the cfi- and pcm-interfaces are not operational. 10 the cm-initialization mode allows fast programming of the control memory since each memory access takes a maximum of only 2.5 rcl-cycles compared to the 9.5 rcl-cycles in the normal mode. accesses are performed on individual addresses specified by maar. the initialization of control/signaling channels in iom- applications can for example be carried out in this mode. in the cm- initialization mode the epic-1 does also not work normally. 11 in the normal operation mode the cfi- and pcm-interfaces are operational. memory accesses performed on single addresses (speci?ed by maar) take 9.5 rcl-cycles. an initialization of the complete data memory tri-state ?eld takes 1035 rcl-cycles. 01 in test mode the epic-1 sustains normal operation. however memory accesses are no longer performed on a specific address defined by maar, but on all locations of the selected memory, the contents of maar (including the u/d-bit!) being ignored. a test mode access takes 2057 rcl-cycles. peb 20560 description of registers semiconductor group 5-55 1997-11-01 psb pcm-standby. 0the pcm-interface output pins txd03 are set to high impedance and those tsc -pins that are actually used as tri-state control signals are set to logical 1 (inactive). 1the pcm-output pins transmit the contents of the upstream data memory or may be set to high impedance via the data memory tri-state field. ptl pcm-test loop. 0the pcm-test loop is disabled. 1the pcm-test loop is enabled, i.e. the physical transmit pins txd# are internally connected to the corresponding physical receive pins rxd#, such that data transmitted over txd# are internally looped back to rxd# and data externally received over rxd# are ignored. the txd# pins still output the contents of the upstream data memory according to the setting of the tri-state field (only modes 0 and 1; mode 1 with ais-bit set). cos dont care. the input driver is determinated in register ccr1:ods of sidec0. mfps monitor/feature control channel protocol selection. 0handshake facility disabled (sld and iom-1 applications) 1handshake facility enabled (iom-2 applications) csb cfi-standby. 0the cfi-interface output pins dd03, du03, dcl and fsc are set to high impedance. 1the cfi-output pins are active. rbs register bank selection. used in demultiplexed data/address modes only. the rbs-bit is internally ored with the a4 address pin. the epic-1 registers can therefore be accessed using two different methods: 1) if rbs is always set to logical 0, the registers can be accessed using all 5 address pins a4a0. peb 20560 description of registers semiconductor group 5-56 1997-11-01 5.1.1.4.33 version number status register (vnsr) access: write reset value: 0x h the vnsr-register bits do not generate interrupts and are not modified by reading vnsr. the ir and vn30 bits are read only bits, the swrx-bit is a write only bit. ir initialization request; this bit is set to logical 1 after an inappropriate clocking or after a power failure. it is reset to logical 0 after a control memory reset command: omdr:oms10 = 00, macr = 7x. swrx software reset external. when set, the pin resin is activated. resin is reset with the next epic-1 interrupt, i.e. the epic-1 timer may be used to generate a resin-pulse without generating an internal elic-reset. x dont care 5.1.1.5 sacco-a register description 5.1.1.5.1 receive fifo (rfifo) access: read) reset value: xx h rd70 receive data 70, data byte received on the serial interface. interrupt controlled data transfer up to 32 bytes of received data can be read from the rfifo following an rpf or an rme interrupt. rpf-interrupt: exactly 32 bytes to be read. rme-interrupt: the number of bytes can be determined reading the registers rbcl, rbch. bit 7 bit 0 ir 0 0 swrx xxxx bit 7 bit 0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 peb 20560 description of registers semiconductor group 5-57 1997-11-01 5.1.1.5.2 transmit fifo (xfifo) access: write reset value: xx h td70 transmit data 70, data byte to be transmitted on the serial interface. interrupt controlled data transfer. up to 32 bytes of transmit data can be written to the xfifo following an xpr-interrupt. 5.1.1.5.3 interrupt status register (ista_a/b) access: read reset value: 00 h rme receive message end. a message of up to 32 bytes or the last part of a message greater then 32 bytes has been received and is now available in the rfifo. the message is complete! the actual message length can be determined by reading the registers rbcl, rbch. rme is not generated when an extended hdlc- frame is recognized in auto-mode (ehc interrupt). rpf receive pool full. a data block of 32 bytes is stored in the rfifo. the message is not yet completed! xpr transmit pool ready. a data block of up to 32 bytes can be written to the xfifo. 5.1.1.5.4 mask register (mask_a/b) access: write reset value: 00 h (all interrupts enabled) rme enables(0)/disables(1) the receive message end interrupt. rpf enables(0)/disables(1) the receive pool full interrupts. bit 7 bit 0 td7 td6 td5 td4 td3 td2 td1 td0 bit 7 bit 0 rmerpf0xpr0000 bit 7 bit 0 rmerpf0xpr0000 peb 20560 description of registers semiconductor group 5-58 1997-11-01 xpr enables(0)/disables(1) the transmit pool ready interrupt. each interrupt source can be selectively masked by setting the respective bit in the mask_a/b-register (bit position corresponding to the ista_a/b-register). masked interrupts are internally stored but not indicated when reading ista_a/b and also not flagged into the top level ista. after releasing the respective mask_a/b-bit they will be indicated again in ista_a/b and in the top level ista. when writing register mask_a/b while ista_a/b indicates a non masked interrupt the int -pin is temporarily set into the inactive state. in this case the interrupt remains indicated in the ista_a/b until these registers are read. 5.1.1.5.5 extended interrupt register (exir_a/b) access: read reset value: 00 h xmr transmit message repeat. the transmission of a frame has to be repeated because: C a frame consisting of more then 32 bytes is polled a second time in auto-mode. C collision has occurred after sending the 32nd data byte of a message in a bus configuration. C cts (transmission enable) has been withdrawn after sending the 32nd data byte of a message in point-to-point configuration. xdu/exe transmission data underrun/extended transmission end. the actual frame has been aborted with idle, because the xfifo holds no further data, but the frame is not yet complete according to registers xbch/xbcl. in extended transparent mode, this bit indicates the transmission end condition. note: it is not possible to transmit frames when a xmr- or xdu-interrupt is indicated. ehc extended hdlc-frame. the sacco has received a frame in auto-mode which is neither a rr- nor an i-frame. the control byte is stored temporarily in the rhcr-register but not in the rfifo. bit 7 bit 0 xmr xdu/exe ehc rfo 0 rfs 0 0 peb 20560 description of registers semiconductor group 5-59 1997-11-01 rfo receive frame overflow. a frame could not be stored due to the occupied rfifo (i.e. whole frame has been lost). this interrupt can be used for statistical purposes and indicates, that the cpu does not respond quickly enough to an incoming rpf- or rme- interrupt. rfs receive frame start. this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after a valid address check in operation modes providing address recognition, otherwise after the opening flag (transparent mode 0), delayed by two bytes. after a rfs-interrupt the contents of ? rhcr ? ral1 ? rsta bit3-0 are valid and can by read by the cpu. the rfs-interrupt is maskable by programming bit ccr2:rie. 5.1.1.5.6 command register (cmdr) access: write reset value: 00 h note: the maximum time between writing to the cmdr-register and the execution of the command is 2.5 hdc-clock cycles. therefore, if the cpu operates with a very high clock speed in comparison to the sacco-clock, it is recommended that the bit star:cec is checked before writing to the cmdr-register to avoid loosing of commands. rmc receive message complete. a 1 confirms, that the actual frame or data block has been fetched following a rpf- or rme-interrupt, thus the occupied space in the rfifo can be released. rhr reset hdlc-receiver. a 1 deletes all data in the rfifo and in the hdlc-receiver. xrep extended transparent mode 0,1: xrep together with xtf- and xme-set (cmdr = 2a h ) the sacco repeatedly transmits the contents of the xfifo (132 bytes) fully transparent without hdlc-framing, i.e. without flag, crc-insertion, bit stuffing. bit 7 bit 0 rmc rhr xrep 0 xpd/ xtf xdd xme xres peb 20560 description of registers semiconductor group 5-60 1997-11-01 the cyclical transmission continues until the command (cmdr:xres) is executed or the bit xrep is reset. the inter frame timefill pattern is issued afterwards. when resetting xrep, data transmission is stopped after the next xfifo- cycle is completed, the xres-command terminates data transmission immediately. note: mode:cft must be set to 0 when using cyclic transmission. xpd/xtf transmit prepared data/transmit transparent frame. ? non-auto-mode, transparent mode 0,1: xtf the transmission of the xfifo contents is started, an opening flag sequence is automatically added. ? extended transparent mode 0,1: xtf the transmission of the xfifo contents is started, no opening flag sequence is added. xme transmit message end (interrupt mode only). a 1 indicate that the data block written last to the xfifo completes the actual frame. the sacco can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. xme is used only in combination with xpd/xtf or xdd. xres transmit reset. the contents of the xfifo is deleted and idle is transmitted. this command can be used by the cpu to abort a frame currently in transmission. after setting xres a xpr-interrupt is generated in every case. 5.1.1.5.7 mode register (mode) access: read/write reset value: 00 h mds10 mode select. the operating mode of the hdlc-controller is selected. 01non-auto-mode 10transparent mode (d-channel arbiter) 11extended transparent mode adm address mode. the meaning of this bit varies depending on the selected operating mode: bit 7 bit 0 mds1 mds0 adm cft rac 0 0 tlp peb 20560 description of registers semiconductor group 5-61 1997-11-01 ? transparent mode 0no address recognition: transparent mode 0 (d-channel arbiter) 1high byte address recognition: transparent mode 1 ? extended transparent mode 0receive data in ral1: extended transparent mode 0 1receive data in rfifo and ral1: extended transparent mode 1 note: in extended transparent mode 0 and 1 the bit mode:rac must be reset to enable fully transparent reception. cft continuous frame transmission. 1when cft is set the xpr-interrupt is generated immediately after the cpu accessible part of xfifo is copied into the transmitter section. 0otherwise the xpr-interrupt is delayed until the transmission is completed (d-channel arbiter). rac receiver active. via rac the hdlc-receiver can be activated/deactivated. 0hdlc-receiver inactive 1hdlc-receiver active in extended transparent mode 0 and 1 rac must be reset (hdlc-receiver disabled) to enable fully transparent reception. tlp test loop. when set input and output of the hdlc-channel are internally connected. (transmitter channel a - receiver channel a transmitter channel b - receiver channel b) txda/b are active, rxda/b are disabled. 5.1.1.5.8 channel configuration register 1 (ccr1) access: read/write reset value: 00 h pu power-down mode. 0power-down (standby), the internal clock is switched off. nevertheless, register read/write access is possible. 1power-up (active). cm2 clock rate 0single clock 1double clock bit 7 bit 0 pu0000cm211 peb 20560 description of registers semiconductor group 5-62 1997-11-01 5.1.1.5.9 channel configuration register 2 (ccr2) access: read/write reset value: 00 h rie receive frame start enable. when set, the rfs-interrupt in register exir_a/b is enabled. 5.1.1.5.10 receive length check register (rlcr) access: write reset value: 0xxxxxxx h rc receive check enable. a 1 enables, a 0 disables the receive frame length feature. rl60 receive length. the maximum receive length after which data reception is suspended can be programmed in rl60. the maximum allowed receive frame length is (rl + 1) 32 bytes. a frame exceeding this length is treated as if it was aborted by the opposite station (rme-interrupt, rab-bit set (vfr )). in this case the receive byte count (rbch, rbcl) is greater than the programmed receive length. 5.1.1.5.11 status register (star) access: read reset value: 48 h xdov transmit data overflow. a 1 indicates, that more than 32 bytes have been written into the xfifo. xfw xfifo write enable. a 1 indicates, that data can be written into the xfifo. note: xfw is only valid when cec = 0. bit 7 bit 0 00000 0 rie 0 bit 7 bit 0 rc rl6 rl5 rl4 rl3 rl2 rl1 rl0 bit 7 bit 0 xdov xfw arep/ xrep rfr rli cec xac afi peb 20560 description of registers semiconductor group 5-63 1997-11-01 xrep read back value of the corresponding command bit cmdr:xrep. rfr rfifo read enable. a 1 indicates, that valid data is in the rfifo and read access is enabled. rfr is set with the rme- or rpf-interrupt and reset when executing the rmc-command. rli receiver line inactive. neither flags as inter frame time fill nor frames are received via the receive line. note: significant in point-to-point configurations! cec command execution. when 0 no command is currently executed, the cmdr-register can be written to. when 1 a command (written previously to cmdr) is currently executed, no further command must temporarily be written to the cmdr-register. xac transmitter active. a 1 indicates, that the transmitter is currently active. afi additional frame indication. a 1 indicates, that one or more completely received frames or the last part of a frame are in the cpu inaccessible part of the rfifo. in combination with the bit star:rfr multiple frames can be read out of the rfifo without interrupt control. 5.1.1.5.12 receive status register (rsta) access: read reset value: xx h rsta always displays the momentary state of the receiver. because this state can differ from the last entry in the fifo it is reasonable to always use the status bytes in the fifo. vfr valid frame. indicates whether the received frame is valid (1) or not (0 invalid). a frame is invalid when C its length is not an integer multiple of 8 bits (n 8 bits), e.g. 25 bit, C its is to short, depending on the selected operation mode: transparent mode 1: 3 bytes transparent mode 0: 2 bytes C a frame was aborted (note: vfr can also be set when a frame was aborted) bit 7 bit 0 vfr rdo crc rab ha1 ha0 c/r la peb 20560 description of registers semiconductor group 5-64 1997-11-01 note: shorter frames are not reported. rdo receive data overflow. a 1 indicates, that a rfifo-overflow has occurred within the actual frame. crc crc-compare check. 0: crc check failed, received frame contains errors. 1: crc check o.k., received frame is error free. rab receive message aborted. when 1 the received frame was aborted from the transmitting station. according to the hdlc-protocol, this frame must be discarded by the cpu. ha10 high byte address compare. in operating modes which provide high byte address recognition, the sacco compares the high byte of a 2-byte address with the contents of two individual programmable registers (rah1, rah2) and the fixed values feh and fch (group address). depending on the result of the comparison, the following bit combinations are possible: 10rah1 has been recognized. 00rah2 has been recognized. 01group address has been recognized. note: if rah1, rah2 contain the identical value, the combination 00 will be omitted. ha1..0 is significant only in 2-byte address modes. c/r command/response; significant only, if 2-byte address mode has been selected. value of the c/r bit (bit of high address byte) in the received frame. la low byte address compare. the low byte address of a 2-byte address field or the single address byte of a 1-byte address field is compared with two programmable registers (ral1, ral2). depending on the result of the comparison la is set. 0ral2 has been recognized, 1ral1 has been recognized. in non-auto mode, according to the x.25 lap b-protocol, ral1/ral2 may be programmed to differ between command/response frames. note: a modified receive status byte is copied into the rfifo following the last byte of the corresponding frame.so contains the iom-port and channel address of the received frame. please refer to chapter 2.1.2.4.6 the rfifo. peb 20560 description of registers semiconductor group 5-65 1997-11-01 5.1.1.5.13 receive hdlc-control register (rhcr) access: read reset value: xx h rhcr70 receive hdlc-control register. the contents of the rhcr depends on the selected operating mode. non-auto mode (1-byte address field): 2nd byte after flag non-auto mode (2-byte address field): 3rd byte after flag transparent mode 1: 3nd byte after flag transparent mode 0: 2nd byte after flag note: the value in rhcr corresponds to the last received frame. 5.1.1.5.14 transmit address byte 1 (xad1) access: write reset value: xx h xad1710 transmit address byte 1. the value stored in xad1 is included automatically as the address byte (high address byte in case of 2-byte address field) of all frames transmitted in auto mode. using a 2 byte address field, xad11 and xad10 have to be set to 0. 5.1.1.5.15 transmit address byte 2 (xad2) access: write reset value: xx h xad2720 transmit address byte 2. the value stored in xad2 is included automatically as the low address byte of all frames transmitted in auto-mode (2-byte address field only). bit 7 bit 0 rhcr7 rhcr6 rhcr5 rhcr4 rhcr3 rhcr2 rhcr1 rhcr0 bit 7 bit 0 xad17 xad16 xad15 xad14 xad13 xad12 xad11 xad10 bit 7 bit 0 xad27 xad26 xad25 xad24 xad23 xad22 xad21 xad20 peb 20560 description of registers semiconductor group 5-66 1997-11-01 5.1.1.5.16 receive address byte low register 1 (ral1) access: read/write reset value: xx h ral1710 receive address byte low register 1. the general function (read/write) and the meaning or contents of this register depends on the selected operating mode: ? non-auto mode (address recognition) - write only: compare value 1, address recognition (low byte in case of 2-byte address field). ? transparent mode 1 (high byte address recognition) - read only: ral1 contains the byte following the high byte of the address in the received frame (i.e. the second byte after the opening flag). ? transparent mode 0 (no address recognition) - read only: contains the first byte after the opening flag (first byte of the received frame). ? extended transparent mode 0,1 - read only: ral1 contains the actual data byte currently assembled at the rxd-pin by passing the hdlc-receiver (fully transparent reception without hdlc-framing). note: in auto-mode and non-auto mode the read back of the programmed value is inverted. 5.1.1.5.17 receive address byte low register 2 (ral2) access: write reset value: xx h ral2720 receive address byte low register 1. ? non-auto mode (address recognition): compare value 2, address recognition (low byte in case of 2-byte address field). note: normally used for broadcast address. bit 7 bit 0 ral17 ral16 ral15 ral14 ral13 ral12 ral11 ral10 bit 7 bit 0 ral27 ral26 ral25 ral24 ral23 ral22 ral21 ral20 peb 20560 description of registers semiconductor group 5-67 1997-11-01 5.1.1.5.18 receive address byte high register 1 (rah1) access: write reset value: xx h ral1712 receiver address byte high register 1. ? non-auto mode transparent mode 1, (2-byte address field). compare value 1, high byte address recognition. note: when a 1-byte address field is used in non-auto or auto-mode, rah1 must be set to 00 h . 5.1.1.5.19 receive address byte high register 2 (rah2) access: write reset value: xx h ral2722 receiver address byte high register 2. ? non-auto mode transparent mode 1, (2-byte address field). compare value 2, high byte address recognition. note: when a 1-byte address field is used in non-auto or auto-mode, rah2 must be set to 00 h . 5.1.1.5.20 receive byte count low (rbcl) access: read reset value: 00 h rbc70 receive byte count. together with rbch (bits rbc11 - rbc8), the length of the actual received frame (04095 bytes) can be determined. these registers must be read by the cpu following a rme interrupt. bit 7 bit 0 rah17 rah16 rah15 rah14 rah13 rah12 0 0 bit 7 bit 0 rah27 rah26 rah25 rah24 rah23 rah22 0 0 bit 7 bit 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 peb 20560 description of registers semiconductor group 5-68 1997-11-01 5.1.1.5.21 receive byte count high (rbch) access: read reset value: 000xxxxx h dma dma-mode status indication. read back value representing the dma-bit programmed in register xbch. ov counter overflow. a 1 indicates that more than 4095 bytes were received. the received frame exceeded the byte count in rbc11rbc0. rbc118 receive byte count high. together with rbcl (bits rbc7rbc0) the length of the received frame can be determined. 5.1.1.5.22 version status register (vstr) access: read vn30 82 h : sacco-a in doc v1.1 83 h : sacco-a in doc v2.1. 5.1.1.6 sacco-b register description 5.1.1.6.1 receive fifo (rfifo) access: read reset value: xx h rd70 receive data 70, data byte received on the serial interface. interrupt controlled data transfer (interrupt mode, selected if dma-bit in register xbch is reset). up to 32 bytes of received data can be read from the rfifo following an rpf or an rme interrupt. bit 7 bit 0 0 0 0 ov rbc11 rbc10 rbc9 rbc8 bit 7 bit 0 1000vn3vn2vn1vn0 bit 7 bit 0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 peb 20560 description of registers semiconductor group 5-69 1997-11-01 rpf-interrupt: exactly 32 bytes to be read. rme-interrupt: the number of bytes can be determined reading the registers rbcl, rbch. dma controlled data transfer (dma-mode, selected if dma-bit in register xbch is set). if the rfifo contains 32 bytes, the sacco autonomously requests a block data transfer by activating the drqra/b-line as long as the 31st read cycle is finished. this forces the dma-controller to continuously perform bus cycles until 32 bytes are transferred from the sacco to the system memory (dma-controller mode: demand transfer, level triggered). if the rfifo contains less than 32 bytes (one short frame or the last bytes of a long frame) the sacco requests a block data transfer depending on the contents of the rfifo according to the following table: additionally an rme-interrupt is issued after the last byte has been transferred. as a result, the dma-controller may transfer more bytes as actually valid in the current received frame. the valid byte count must therefore be determined reading the registers rbch, rbcl following the rme-interrupt. the corresponding drqra/b pin remains high as long as the rfifo requires data transfers. it is deactivated upon the rising edge of the 31st dma-transfer or, if n < 32 or n is the remainder of a long frame, upon the falling edge of the last dma-transfer. if n 3 32 and the dma-controller does not perform the 32nd dma-cycle, the drqra/b-line will go high again as soon as css goes high, thus indicating further bytes to fetch. 5.1.1.6.2 transmit fifo (xfifo) access: write reset value: xx h table 5-46 rfifo contents (bytes) dma transfers (bytes) (1), 2, 3 4 4 - 7 8 8 - 15 16 16 - 32 32 bit 7 bit 0 td7 td6 td5 td4 td3 td2 td1 td0 peb 20560 description of registers semiconductor group 5-70 1997-11-01 td70 transmit data 70, data byte to be transmitted on the serial interface. interrupt controlled data transfer (interrupt mode, selected if dma-bit in register xbch is reset). up to 32 bytes of transmit data can be written to the xfifo following an xpr-interrupt. dma controlled data transfer (dma-mode, selected if dma-bit in register xbch is set). prior to any data transfer, the actual byte count of the frame to be transmitted must be written to the registers xbch, xbcl: 1 byte: xbcl = 0 n bytes: xbcl = n - 1 if a data transfer is then initiated via the cmdr-register (commands xpd/xtf or xdd), the sacco autonomously requests the correct amount of block data transfers (n 32 + remainder, n = 0,1, ). the corresponding drqta/b pin remains high as long as the xfifo requires data transfers. it is deactivated upon the rising edge of wr in the dma-transfer 31 or n - 1 respectively. the dma-controller must take care to perform the last dma-transfer. if it is missing, the drqta/b-line will go active again when css is raised. 5.1.1.6.3 interrupt status register (ista_a/b) access: read reset value: 00 h rme receive message end. a message of up to 32 bytes or the last part of a message greater then 32 bytes has been received and is now available in the rfifo. the message is complete! the actual message length can be determined by reading the registers rbcl, rbch. rme is not generated when an extended hdlc- frame is recognized in auto-mode (ehc interrupt). in dma-mode a rme-interrupt is generated after the dma-transfer has been finished correctly, indicating that the processor should read the registers rbch/rbcl to determine the correct message length. rpf receive pool full. a data block of 32 bytes is stored in the rfifo. the message is not yet completed! note: this interrupt is only generated in interrupt mode (not in dma-mode). bit 7 bit 0 rmerpf0xpr0000 peb 20560 description of registers semiconductor group 5-71 1997-11-01 xpr transmit pool ready. a data block of up to 32 bytes can be written to the xfifo. 5.1.1.6.4 mask register (mask_a/b) access: write reset value: 00 h (all interrupts enabled) rme enables(0)/disables(1) the receive message end interrupt. rpf enables(0)/disables(1) the receive pool full interrupts. xpr enables(0)/disables(1) the transmit pool ready interrupt. each interrupt source can be selectively masked by setting the respective bit in the mask_a/b-register (bit position corresponding to the ista_a/b-register). masked interrupts are internally stored but not indicated when reading ista_a/b and also not flagged into the top level ista. after releasing the respective mask_a/b-bit they will be indicated again in ista_a/b and in the top level ista. when writing register mask_a/b while ista_a/b indicates a non masked interrupt the int -pin is temporarily set into the inactive state. in this case the interrupt remains indicated in the ista_a/b until these registers are read. 5.1.1.6.5 extended interrupt register (exir_a/b) access: read reset value: 00 h xmr transmit message repeat. the transmission of a frame has to be repeated because: C a frame consisting of more then 32 bytes is polled a second time in auto-mode. C collision has occurred after sending the 32nd data byte of a message in a bus configuration. C cts (transmission enable) has been withdrawn after sending the 32nd data byte of a message in point-to-point configuration. xdu/exe transmission data underrun/extended transmission end. the actual frame has been aborted with idle, because the xfifo holds no further data, but the frame is not yet complete according to registers bit 7 bit 0 rmerpf0xpr0000 bit 7 bit 0 xmr xdu/exe ehc rfo 0 rfs 0 0 peb 20560 description of registers semiconductor group 5-72 1997-11-01 xbch/xbcl. in extended transparent mode, this bit indicates the transmission end condition. it is not possible to transmit frames when a xmr- or xdu-interrupt is indicated. ehc extended hdlc-frame. the sacco has received a frame in auto-mode which is neither a rr- nor an i-frame. the control byte is stored temporarily in the rhcr-register but not in the rfifo. rfo receive frame overflow. a frame could not be stored due to the occupied rfifo (i.e. whole frame has been lost). this interrupt can be used for statistical purposes and indicates, that the cpu does not respond quickly enough to an incoming rpf- or rme- interrupt. rfs receive frame start. this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after a valid address check in operation modes providing address recognition, otherwise after the opening flag (transparent mode 0), delayed by two bytes. after a rfs-interrupt the contents of rhcr ral1 rsta bit3-0 are valid and can by read by the cpu. the rfs-interrupt is maskable by programming bit ccr2:rie. 5.1.1.6.6 command register (cmdr) access: write reset value: 00 h note: the maximum time between writing to the cmdr-register and the execution of the command is 2.5 hdc-clock cycles. therefore, if the cpu operates with a very high clock speed in comparison to the sacco-clock, it is recommended that the bit star:cec is checked before writing to the cmdr-register to avoid loosing of commands. rmc receive message complete. a 1 confirms, that the actual frame or data block has been fetched following bit 7 bit 0 rmc rhr arep/ xrep 0 xpd/ xtf xdd xme xres peb 20560 description of registers semiconductor group 5-73 1997-11-01 a rpf- or rme-interrupt, thus the occupied space in the rfifo can be released. note: in dma-mode this command is only issued once after a rme-interrupt. the sacco does not generate further dma requests prior to the reception of this command. rhr reset hdlc-receiver. a 1 deletes all data in the rfifo and in the hdlc-receiver. arep/ auto repeat/transmission repeat. xrep auto-mode: arep ? the frame (max. length 32 byte) stored in xfifo can be polled repeatedly by the opposite station until the frame is acknowledged. ? extended transparent mode 0,1: xrep together with xtf- and xme-set (cmdr = 2a h ) the sacco repeatedly transmits the contents of the xfifo (132 bytes) fully transparent without hdlc-framing, i.e. without flag, crc-insertion, bit stuffing. the cyclical transmission continues until the command (cmdr:xres) is executed or the bit xrep is reset. the inter frame timefill pattern is issued afterwards. when resetting xrep, data transmission is stopped after the next xfifo- cycle is completed, the xres-command terminates data transmission immediately. note: mode:cft must be set to 0 when using cyclic transmission. xpd/xtf transmit prepared data/transmit transparent frame. ? auto-mode: xpd prepares the transmission of an i-frame (prepared data) in auto-mode. the actual transmission starts, when the sacco receives an i-frame with poll-bit set and axh as the first data byte (pbc-command transmit prepared data). upon the reception of a different poll frame a response is generated automatically (rr-poll t rr-response, i-poll with first byte not axh t i-response). ? non-auto-mode, transparent mode 0,1: xtf the transmission of the xfifo contents is started, an opening flag sequence is automatically added. ? extended transparent mode 0,1: xtf the transmission of the xfifo contents is started, no opening flag sequence is added. xdd transmit direct data (auto-mode only!). prepares the transmission of an i-frame (direct data) in auto-mode. the actual transmission starts, when the sacco receives a rr-frame with peb 20560 description of registers semiconductor group 5-74 1997-11-01 poll-bit set. upon the reception of an i-frame with poll-bit set, an i-response is issued. xme transmit message end (interrupt mode only). a 1 indicate that the data block written last to the xfifo completes the actual frame. the sacco can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. xme is used only in combination with xpd/xtf or xdd. note: when using the dma-mode xme must not be used. xres transmit reset. the contents of the xfifo is deleted and idle is transmitted. this command can be used by the cpu to abort a frame currently in transmission. after setting xres a xpr-interrupt is generated in every case. 5.1.1.6.7 mode register (mode) access: read/write reset value: 00 h mds10 mode select. the operating mode of the hdlc-controller is selected. 00auto-mode 01non-auto-mode 11extended transparent mode adm address mode. the meaning of this bit varies depending on the selected operating mode: ? auto-mode / non-auto mode defines the length of the hdlc-address field. 08-bit address field, 116-bit address field. ? transparent mode 0 no address recognition: transparent mode 0 (d-channel arbiter) 1 high byte address recognition: transparent mode 1 ? extended transparent mode 0 receive data in ral1: extended transparent mode 0 1 receive data in rfifo and ral1: extended transparent mode 1 note: in extended transparent mode 0 and 1 the bit mode:rac must be reset to enable fully transparent reception. bit 7 bit 0 mds1 mds0 adm cft rac 0 0 tlp peb 20560 description of registers semiconductor group 5-75 1997-11-01 cft continuous frame transmission. 1when cft is set the xpr-interrupt is generated immediately after the cpu accessible part of xfifo is copied into the transmitter section. 0otherwise the xpr-interrupt is delayed until the transmission is completed (d-channel arbiter). rac receiver active. via rac the hdlc-receiver can be activated/deactivated. 0hdlc-receiver inactive 1hdlc-receiver active in extended transparent mode 0 and 1 rac must be reset (hdlc-receiver disabled) to enable fully transparent reception. tlp test loop. when set input and output of the hdlc-channel are internally connected. (transmitter channel a - receiver channel a transmitter channel b - receiver channel b) txda/b are active, rxda/b are disabled. 5.1.1.6.8 channel configuration register 1 (ccr1) access: read/write reset value: 00 h pu power-down mode. 0power-down (standby), the internal clock is switched off. nevertheless, register read/write access is possible. 1power-up (active). sc10 serial port configuration. 00point to point configuration, 01bus configuration, timing mode 1, data is output with the rising edge of the data clock on pin txda/b and evaluated 1/2 clock period later with the falling clock edge at pin cxda/b. 11bus configuration, timing mode 2, data is output with the falling edge of the data clock and evaluated with the next falling clock edge. thus one complete clock period is available between data output and evaluation. ods output driver select. (only valid if configurated in stand-alone mode. when connected to iom or pcm sign.mux, ccr1:ods of sidec0 defines the output driver). bit 7 bit 0 pu sc1 sc0 ods itf cm2 cm1 cm0 peb 20560 description of registers semiconductor group 5-76 1997-11-01 defines the function of the transmit data pin (txda/b). 0txda/b-pin open drain output 1txda/b-pin push-pull output up to version 1.2 when selecting a bus configuration only the open drain option must be selected. compared to the version 1.2 the version 1.3 provides new features: push-pull operation may be selected in bus configuration (up to version 1.2 only open drain): ? when active txda / txdb outputs serial data in push-pull-mode ? when inactive (interframe or inactive timeslots) txda / txdb outputs 1 note: when bus configuration with direct connection of multiple elics is used open drain option is still recommended. the push-pull option with bus configuration can only be used if an external tri-state buffer is placed between txda / txdb and the bus. due to the delay of tsca / tscb in this mode (see description of bits soc(0:1) in register ccr2 ( chapter 5.1.1.5.9 ) these signals cannot directly be used to enable this buffer. itf inter frame time fill. determines the no data to send state of the transmit data pin (txda/b). 0continuous idle-sequences are output (11111111 bit pattern). in a bus configuration (ccr1:sc0 = 1) itf is implicitly set to 0 (continuous 1s are transmitted). 1continuous flag-sequences are output (01111110 bit pattern). in a bus configuration (ccr1:sc0 = 1) itf is implicitly set to 0 (continuous 1s are transmitted). note: itf has to be set 0 if clock mode 3 is used. cm2 clock rate. 0single rate data clock 1double rate data clock cm10 clock mode. determines the mode in which the data clock is forwarded toward the receiver/transmitter. 00clock mode 0: external data clock, permanently enabled. 01clock mode 1: external data clock, gated by an enable strobe forwarded via pin hfs. 10clock mode 2: external data clock, programmable time-slot assignment, frame synchronization pulse forwarded via pin hfs. 11not allowed peb 20560 description of registers semiconductor group 5-77 1997-11-01 5.1.1.6.9 channel configuration register 2 (ccr2) access: read/write reset value: 00 h soc1, soc0 the function of the tsca/b-pin can be defined programming soc1,soc0. ? bus configuration: 00the tsca/b output is activated only during the transmission of a frame delayed by one clock period. when transmission was stopped due to a collision tsca/b remains inactive . 10the tsca/b-output is always high (disabled). 11the tsca/b-output indicates the reception of a data frame (active low) ? point-to-point configuration: 0xthe tsca/b-output is activated during the transmission of a frame. 1xthe tsca/b-output is activated during the transmission of a frame and of inter frame timefill. xcs0 transmit/receive clock shift, bit 0 (only clock mode 2). rcs0 together with the bits xcs2, xcs1 (rcs2, rcs1) in tsax (tsar) the clock shift relative to the frame synchronization signal of the transmit (receive) time-slot can be adjusted. a clock shift of 07 bits is programmable (clock mode 2 only!). note: in the clock modes 0,1 and 3 xcs0 and rcs0 has to be set to '0'. txde transmit data enable. 0the pin txda/b is disabled (in the state high impedance). 1the pin txda/b is enabled. depending on the programming of bit ccr1:ods it has a push pull or open drain characteristic. rds receive data sampling. 0 : serial data on rxda/b is sampled at the falling edge of hdca/b. 1 : serial data on rxda/b is sampled at the rising edge of hdca/b. note: with rds = 1 the sampling edge is shifted 1/2 clock phase forward. the data is internally still processed with the falling edge. rie receive frame start enable. when set, the rfs-interrupt in register exir_a/b is enabled. bit 7 bit 0 soc1 soc0 xcs0 rcs0 txde rds rie 0 peb 20560 description of registers semiconductor group 5-78 1997-11-01 5.1.1.6.10 receive length check register (rlcr) access: write reset value: 0xxxxxxx h rc receive check enable. a 1 enables, a 0 disables the receive frame length feature. rl60 receive length. the maximum receive length after which data reception is suspended can be programmed in rl60. the maximum allowed receive frame length is (rl + 1) 32 bytes. a frame exceeding this length is treated as if it was aborted by the opposite station (rme-interrupt, rab-bit set (vfr in clock mode 3)). in this case the receive byte count (rbch, rbcl) is greater than the programmed receive length. 5.1.1.6.11 status register (star) access: read reset value: 48 h xdov transmit data overflow. a 1 indicates, that more than 32 bytes have been written into the xfifo. xfw xfifo write enable. a 1 indicates, that data can be written into the xfifo. note: xfw is only valid when cec = 0. arep/ auto repeat/transmission repeat. xrep read back value of the corresponding command bit cmdr:arep/xrep. rfr rfifo read enable. a 1 indicates, that valid data is in the rfifo and read access is enabled. rfr is set with the rme- or rpf-interrupt and reset when executing the rmc-command. bit 7 bit 0 rc rl6 rl5 rl4 rl3 rl2 rl1 rl0 bit 7 bit 0 xdov xfw arep/ xrep rfr rli cec xac afi peb 20560 description of registers semiconductor group 5-79 1997-11-01 rli receiver line inactive. neither flags as inter frame time fill nor frames are received via the receive line. note: significant in point-to-point configurations! cec command execution. when 0 no command is currently executed, the cmdr-register can be written to. when 1 a command (written previously to cmdr) is currently executed, no further command must temporarily be written to the cmdr-register. xac transmitter active. a 1 indicates, that the transmitter is currently active. in bus mode the transmitter is considered active also when it waits for bus access. afi additional frame indication. a 1 indicates, that one or more completely received frames or the last part of a frame are in the cpu inaccessible part of the rfifo. in combination with the bit star:rfr multiple frames can be read out of the rfifo without interrupt control. 5.1.1.6.12 receive status register (rsta) access: read reset value: xx h rsta always displays the momentary state of the receiver. because this state can differ from the last entry in the fifo it is reasonable to always use the status bytes in the fifo. vfr valid frame. indicates whether the received frame is valid (1) or not (0 invalid). a frame is invalid when C its length is not an integer multiple of 8 bits (n 8 bits), e.g. 25 bit, C its is to short, depending on the selected operation mode: auto-mode/non-auto mode (2-byte address field): 4 bytes auto-mode/non-auto mode (1-byte address field): 3 bytes transparent mode 1: 3 bytes transparent mode 0: 2 bytes C a frame was aborted (note: vfr can also be set when a frame was aborted) note: shorter frames are not reported. bit 7 bit 0 vfr rdo crc rab ha1 ha0 c/r la peb 20560 description of registers semiconductor group 5-80 1997-11-01 rdo receive data overflow. a 1 indicates, that a rfifo-overflow has occurred within the actual frame. crc crc-compare check. 0: crc check failed, received frame contains errors. 1: crc check o.k., received frame is error free. rab receive message aborted. when 1 the received frame was aborted from the transmitting station. according to the hdlc-protocol, this frame must be discarded by the cpu. ha10 high byte address compare. in operating modes which provide high byte address recognition, the sacco compares the high byte of a 2-byte address with the contents of two individual programmable registers (rah1, rah2) and the fixed values feh and fch (group address). depending on the result of the comparison, the following bit combinations are possible: 10rah1 has been recognized. 00rah2 has been recognized. 01group address has been recognized. note: if rah1, rah2 contain the identical value, the combination 00 will be omitted. ha1 0 is significant only in 2-byte address modes. c/r command/response; significant only, if 2-byte address mode has been selected. value of the c/r bit (bit of high address byte) in the received frame. la low byte address compare. the low byte address of a 2-byte address field or the single address byte of a 1-byte address field is compared with two programmable registers (ral1, ral2). depending on the result of the comparison la is set. 0ral2 has been recognized, 1ral1 has been recognized. in non-auto mode, according to the x.25 lap b-protocol, ral1/ral2 may be programmed to differ between command/response frames. note: the receive status byte is duplicated into the rfifo (clock mode 0-2) following the last byte of the corresponding frame. peb 20560 description of registers semiconductor group 5-81 1997-11-01 5.1.1.6.13 receive hdlc-control register (rhcr) access: read reset value: xx h rhcr70 receive hdlc-control register. the contents of the rhcr depends on the selected operating mode. ? auto-mode (1- or 2-byte address field): i-frame compressed control field (bit 7-4: bit 7-4 of pbc-command, bit 3-0: bit 3-0 of hdlc-control field) else hdlc-control field note: rr-frames and i-frames with the first byte = axh (pbccommand transmit prepared data) are handled automatically and are not transferred to the cpu (no interrupt is issued). ? non-auto mode (1-byte address field): 2nd byte after flag ? non-auto mode (2-byte address field): 3rd byte after flag ? transparent mode 1: 3nd byte after flag ? transparent mode 0: 2nd byte after flag note: the value in rhcr corresponds to the last received frame. 5.1.1.6.14 transmit address byte 1 (xad1) access: write reset value: xx h xad1710 transmit address byte 1. the value stored in xad1 is included automatically as the address byte (high address byte in case of 2-byte address field) of all frames transmitted in auto mode. using a 2 byte address field, xad11 and xad10 have to be set to '0'. bit 7 bit 0 rhcr7 rhcr6 rhcr5 rhcr4 rhcr3 rhcr2 rhcr1 rhcr0 bit 7 bit 0 xad17 xad16 xad15 xad14 xad13 xad12 xad11 xad10 peb 20560 description of registers semiconductor group 5-82 1997-11-01 5.1.1.6.15 transmit address byte 2 (xad2) access: write reset value: xx h xad2720 transmit address byte 2. the value stored in xad2 is included automatically as the low address byte of all frames transmitted in auto-mode (2-byte address field only). 5.1.1.6.16 receive address byte low register 1 (ral1) access: read/write reset value: xx h ral1710 receive address byte low register 1. the general function (read/write) and the meaning or contents of this register depends on the selected operating mode: ? auto-mode, non-auto mode (address recognition) - write only: compare value 1, address recognition (low byte in case of 2-byte address field). ? transparent mode 1 (high byte address recognition) - read only: ral1 contains the byte following the high byte of the address in the received frame (i.e. the second byte after the opening flag). ? transparent mode 0 (no address recognition) - read only: contains the first byte after the opening flag (first byte of the received frame). ? extended transparent mode 0,1 - read only: ral1 contains the actual data byte currently assembled at the rxd-pin by passing the hdlc-receiver (fully transparent reception without hdlc-framing). note: in auto-mode and non-auto mode the read back of the programmed value is inverted. bit 7 bit 0 xad27 xad26 xad25 xad24 xad23 xad22 xad21 xad20 bit 7 bit 0 ral17 ral16 ral15 ral14 ral13 ral12 ral11 ral10 peb 20560 description of registers semiconductor group 5-83 1997-11-01 5.1.1.6.17 receive address byte low register 2 (ral2) access: write reset value: xx h ral2720 receive address byte low register 1. ? auto-mode, non-auto mode (address recognition): compare value 2, address recognition (low byte in case of 2-byte address field). note: normally used for broadcast address. 5.1.1.6.18 receive address byte high register 1 (rah1) access: write reset value: xx h rah1712 receiver address byte high register 1. ? auto-mode, non-auto mode transparent mode 1, (2-byte address field). compare value 1, high byte address recognition. note: when a 1-byte address field is used in non-auto or auto-mode, rah1 must be set to 00 h . 5.1.1.6.19 receive address byte high register 2 (rah2) access: write reset value: xx h rah2722 receiver address byte high register 2. ? auto-mode, non-auto mode transparent mode 1, (2-byte address field). compare value 2, high byte address recognition. note: when a 1-byte address field is used in non-auto or auto-mode, rah2 must be set to 00 h . bit 7 bit 0 ral27 ral26 ral25 ral24 ral23 ral22 ral21 ral20 bit 7 bit 0 rah17 rah16 rah15 rah14 rah13 rah12 0 0 bit 7 bit 0 rah27 rah26 rah25 rah24 rah23 rah22 0 0 peb 20560 description of registers semiconductor group 5-84 1997-11-01 5.1.1.6.20 receive byte count low (rbcl) access: read reset value: 00 h rbc70 receive byte count. together with rbch (bits rbc11 - rbc8), the length of the actual received frame (04095 bytes) can be determined. these registers must be read by the cpu following a rme interrupt. 5.1.1.6.21 receive byte count high (rbch) access: read reset value: 000xxxxx h dma dma-mode status indication. read back value representing the dma-bit programmed in register xbch. ov counter overflow. a 1 indicates that more than 4095 bytes were received. the received frame exceeded the byte count in rbc11rbc0. rbc118 receive byte count high. together with rbcl (bits rbc7rbc0) the length of the received frame can be determined. 5.1.1.6.22 transmit byte count low (xbcl) access: write reset value: xx h xbc70 together with xbch (bits xbc11xbc8) this register is used in dma- mode to program the length of the next frame to be transmitted (14096 bytes). the number of transmitted bytes is xbc + 1. consequently the sacco can request the correct number of dma-cycles after a xdd/xtf- or xdd-command. bit 7 bit 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 bit 7 bit 0 dma 0 0 ov rbc11 rbc10 rbc9 rbc8 bit 7 bit 0 xbc7 xbc6 xbc5 xbc4 xbc3 xbc2 xbc1 xbc0 peb 20560 description of registers semiconductor group 5-85 1997-11-01 5.1.1.6.23 transmit byte count high (xbch) access: write reset value: 0000xxxx h dma dma-mode. selects the data transfer mode between the sacco fifos and the system memory: 0interrupt controlled data transfer (interrupt mode). 1dma controlled data transfer (dma-mode). xc transmit continuously. when xc is set the sacco continuously requests for transmit data ignoring the transmit byte count programmed in register xbch and xbcl. note: only valid in dma-mode. xbc118 transmit byte count high. together with xbc7xbc0 the length of the next frame to be transmitted in dma-mode is determined (14096 bytes). 5.1.1.6.24 time-slot assignment register transmit (tsax) access: write reset value: xx h tsnx50 time-slot number transmit. selects one of up to 64 time-slots (00 h - 3f h ) in which data is transmitted in clock mode 2. the number of bits per time-slot is programmable in register xccr. xcs21 transmit clock shift bit2-1. together with xcs0 in register ccr2 the transmit clock shift can be adjusted in clock mode 2. bit 7 bit 0 dma 0 0 xc xbc11 xbc10 xbc9 xbc8 bit 7 bit 0 tsnx5 tsnx4 tsnx3 tsnx2 tsnx1 tsnx0 xcs2 xcs1 peb 20560 description of registers semiconductor group 5-86 1997-11-01 5.1.1.6.25 time-slot assignment register receive (tsar) access: write reset value: xx h tsnr50 time-slot number receive. selects one of up to 64 time-slots (00 h - 3f h ) in which data is received in clock mode 2. the number of bits per time-slot is programmable in register rccr. rcs21 receive clock shift bit2-1. together with rcs0 in register ccr2 the transmit clock shift can be adjusted in clock mode 2. 5.1.1.6.26 transmit channel capacity register (xccr) access: write reset value: 00 h xbc70 transmit bit count. defines the number of bits to be transmitted in a time-slot in clock mode 2 (number of bits per time-slot = xbc + 1 (1256 bits/time-slot)). note: in extended transparent mode the width of the time-slot has to be n 8 bits. 5.1.1.6.27 receive channel capacity register (rccr) access: write reset value: 00 h rbc70 receive bit count. defines the number of bits to be received in a time-slot in clock mode 2. number of bits per time-slot = rbc + 1 (1256 bits/time-slot). note: in extended transparent mode the width of the time-slot has to be n 8 bits. bit 7 bit 0 tsnr5 tsnr4 tsnr3 tsnr2 tsnr1 tsnr0 rcs2 rcs1 bit 7 bit 0 xbc7 xbc6 xbc5 xbc4 xbc3 xbc2 xbc1 xbc0 bit 7 bit 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 peb 20560 description of registers semiconductor group 5-87 1997-11-01 5.1.1.6.28 version status register (vstr) access: read vn30 sacco version number. 82 h sacco-b in doc v1.1. 83 h sacco-b in doc v2.1. 5.1.1.7 d-channel arbiter registers 5.1.1.7.1 arbiter mode register (amo) access: read/write reset value: 00 h fcc40 full selection counter. the value (fcc40 + 1) defines the number of iom-frames before the arbiter state machine changes from the state limited selection to the state full selection, if the asm does not detect any '0' on the remaining serial input lines (d-channels). e.g. max. delay = 9 frames t amo:fcc40 = 01000. note: to avoid arbiter locking, either a) the state limited selection can be skipped by setting fcc4 0 = 00 h , or b) the fcc4 0 value must be greater than the value described in chapter 2.1.2.5.3 . sca suspend counter activation. 0the suspend counter controls the arbiter state machine. 1the suspend counter is disabled (e.g. for control by m p). cchh control channel handling. the control channel takes place: 0in the c/i channel 1in the mr bit (monitor channel receive bit) cchm control channel master activation. 0disables the control channel master. when disabled, all channels enabled in the dce0-3 registers are sent the available information even when the sacco-a is currently not bit 7 bit 0 1000vn3vn2vn1vn0 bit 7 bit 0 fcc4 fcc3 fcc2 fcc1 fcc0 sca cchh cchm peb 20560 description of registers semiconductor group 5-88 1997-11-01 available. 1enables the control channel master. during reception of d-channel data from a channel which has been enabled in the dce0-3 registers all other enabled channels are sent the blocked information from the control memory (cm). note: the d-channel arbiter can only be operated with fsc framing control modes 3, 6 and 7. 5.1.1.7.2 arbiter state register (astate) access: read reset value: 00 h as20 arbiter (receive channel selector) state: 000 : suspended 100 : full selection 011 : limited selection 001 : expect frame 010 : receive frame pad10 port address. the related frame was received on iom-port pad10 chad20 channel address. the related frame was received in iom-channel chad20. 5.1.1.7.3 suspend counter value register (scv) access: read/write reset value: 00 h scv70 suspend counter value. the value (scv70 + 1) 32 de?nes the number of d-bits which are analyzed in the state expect frame before the arbiter enters the state suspended state and an interrupt is issued. min.: 32 d-bits (16 frames), max: 8192 d-bits. bit 7 bit 0 as2 as1 as0 pad1 pad0 chad2 chad1 chad0 bit 7 bit 0 scv7 scv6 scv5 scv4 scv3 scv2 scv1 scv0 peb 20560 description of registers semiconductor group 5-89 1997-11-01 5.1.1.7.4 d-channel enable register iom ? -port 0 (dce0) access: read/write reset value: 00 h 5.1.1.7.5 d-channel enable register iom ? -port 1 (dce1) access: read/write reset value: 00 h 5.1.1.7.6 d-channel enable register iom ? -port 2 (dce2) access: read/write reset value: 00 h 5.1.1.7.7 d-channel enable register iom ? -port 3 (dce3) access: read/write reset value: 00 h dcen70 d-channel enable bits channel 7-0, iom-port n. 0d-channel i on iom-port n is disabled for data reception. the control channel of a disabled d-channel is not manipulated by the control channel master. it passes the value stored in the epic-1 control memory (c/i or mr must = blocked). the disabling of a d-channel has an immediate effect also when the channel is active. in this case the transmitter (hdlc-controller in the subscriber terminal) is forced to abort the current frame. 1d-channel i on iom-port n is enabled for data reception. the control channel of an enabled d-channel is manipulated a) by the control channel master, if amo:cchm = 1, b) directly via dce, if amo:cchm = 0. bit 7 bit 0 dce07 dce06 dce05 dce04 dce03 dce02 dce01 dce00 bit 7 bit 0 dce17 dce16 dce15 dce14 dce13 dce12 dce11 dce10 bit 7 bit 0 dce27 dce26 dce25 dce24 dce23 dce22 dce21 dce20 bit 7 bit 0 dce37 dce36 dce35 dce34 dce33 dce32 dce31 dce30 peb 20560 description of registers semiconductor group 5-90 1997-11-01 note: when elic1 is connected to iom-2 port 4 to 7 the value for n is iom port number minus 4. 5.1.1.7.8 transmit d-channel address register (xdc) access: read/write reset value: 00 h bct broadcast transmission, bct = 1 enables broadcast transmission. the transmitted frame is send to all channels enabled in the registers bcg0-3. pad10 port address, defines the transmit iom-port when bct = 0. note: when elic1 is connected to iom-2 port 4 to 7 the value for n is iom port number minus 4. chad20 channel address, defines the transmit iom-channel when bct = 0. 5.1.1.7.9 broadcast group iom ? -port 0 (bcg0) access: read/write reset value: 00 h 5.1.1.7.10 broadcast group iom ? -port 1 (bcg1) access: read/write reset value: 00 h 5.1.1.7.11 broadcast group iom ? -port 2 (bcg2) access: read/write reset value: 00 h bit 7 bit 0 0 0 bct pad1 pad0 chad2 chad1 chad0 bit 7 bit 0 bce07 bce06 bce05 bce04 bce03 bce02 bce01 bce00 bit 7 bit 0 bce17 bce16 bce15 bce14 bce13 bce12 bce11 bce10 bit 7 bit 0 bce27 bce26 bce25 bce24 bce23 bce22 bce21 bce20 peb 20560 description of registers semiconductor group 5-91 1997-11-01 5.1.1.7.12 broadcast group iom ? -port 3 (bcg3) access: read/write reset value: 00 h bcen70 broadcast enable bit channel 7-0, iom-port n. bceni: 0d-channel i, iom-port n is disabled for broadcast transmission. 1d-channel i, iom-port n is enabled for broadcast transmission. note: when elic1 is connected to iom-2 port 4 to 7 the value for n is iom port number minus 4. 5.1.2 sidec register description the sidec contains 4 identical hdlc controllers: sacco-n. 5.1.2.1 receive fifo (rfifo) access: read reset value: xx h rd70 receive data 70, data byte received on the serial interface. interrupt controlled data transfer up to 32 bytes of received data can be read from the rfifo following an rpf or an rme interrupt. rpf-interrupt: exactly 32 bytes to be read. rme-interrupt: the number of bytes can be determined reading the registers rbcl, rbch. 5.1.2.2 transmit fifo (xfifo) access: write reset value: xx h bit 7 bit 0 bce37 bce36 bce35 bce34 bce33 bce32 bce31 bce30 bit 7 bit 0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 bit 7 bit 0 td7 td6 td5 td4 td3 td2 td1 td0 peb 20560 description of registers semiconductor group 5-92 1997-11-01 td70 transmit data 70, data byte to be transmitted on the serial interface. interrupt controlled data transfer. up to 32 bytes of transmit data can be written to the xfifo following an xpr-interrupt. 5.1.2.3 interrupt status register (ista_a/b) access: read reset value: 00 h rme receive message end. a message of up to 32 bytes or the last part of a message greater then 32 bytes has been received and is now available in the rfifo. the message is complete! the actual message length can be determined by reading the registers rbcl, rbch. rme is not generated when an extended hdlc- frame is recognized in auto-mode (ehc interrupt). rpf receive pool full. a data block of 32 bytes is stored in the rfifo. the message is not yet completed! xpr transmit pool ready. a data block of up to 32 bytes can be written to the xfifo. 5.1.2.4 mask register (mask_a/b) access: write reset value: 00 h (all interrupts enabled) rme enables(0)/disables(1) the receive message end interrupt. rpf enables(0)/disables(1) the receive pool full interrupts. xpr enables(0)/disables(1) the transmit pool ready interrupt. each interrupt source can be selectively masked by setting the respective bit in the mask_a/b-register (bit position corresponding to the ista_a/b-register). masked interrupts are internally stored but not indicated when reading ista_a/b and also not flagged into the top level ista. after releasing the respective mask_a/b-bit they will be indicated again in ista_a/b and in the top level ista. bit 7 bit 0 rmerpf0xpr0000 bit 7 bit 0 rmerpf0xpr0000 peb 20560 description of registers semiconductor group 5-93 1997-11-01 when writing register mask_a/b while ista_a/b indicates a non masked interrupt the int -pin is temporarily set into the inactive state. in this case the interrupt remains indicated in the ista_a/b until these registers are read. 5.1.2.5 extended interrupt register (exir_a/b) access: read reset value: 00 h xmr transmit message repeat. the transmission of a frame has to be repeated because: C a frame consisting of more then 32 bytes is polled a second time in auto-mode. C collision has occurred after sending the 32nd data byte of a message in a bus configuration. C cts (transmission enable) has been withdrawn after sending the 32nd data byte of a message in point-to-point configuration. xdu/exe transmission data underrun/extended transmission end. the actual frame has been aborted with idle, because the xfifo holds no further data, but the frame is not yet complete according to registers xbch/xbcl. in extended transparent mode, this bit indicates the transmission end condition. note: it is not possible to transmit frames when a xmr- or xdu-interrupt is indicated. ehc extended hdlc-frame. the sacco has received a frame in auto-mode which is neither a rr- nor an i-frame. the control byte is stored temporarily in the rhcr-register but not in the rfifo. rfo receive frame overflow. a frame could not be stored due to the occupied rfifo (i.e. whole frame has been lost). this interrupt can be used for statistical purposes and indicates, that the cpu does not respond quickly enough to an incoming rpf- or rme- interrupt. rfs receive frame start. this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after a valid address check in operation modes providing address recognition, otherwise after the opening flag (transparent mode 0), delayed by two bytes. bit 7 bit 0 xmr xdu/exe ehc rfo 0 rfs 0 0 peb 20560 description of registers semiconductor group 5-94 1997-11-01 after a rfs-interrupt the contents of rhcr ral1 rsta bit3-0 are valid and can by read by the cpu. the rfs-interrupt is maskable by programming bit ccr2:rie. 5.1.2.6 command register (cmdr) access: write reset value: 00 h note: the maximum time between writing to the cmdr-register and the execution of the command is 2 bits clocks. therefore, if the cpu operates with a very high clock speed in comparison to the sacco-clock, it is recommended that the bit star:cec is checked before writing to the cmdr-register to avoid loosing of commands. rmc receive message complete. a 1 confirms, that the actual frame or data block has been fetched following a rpf- or rme-interrupt, thus the occupied space in the rfifo can be released. rhr reset hdlc-receiver. a 1 deletes all data in the rfifo and in the hdlc-receiver. arep/ auto repeat/transmission repeat. xrep auto-mode: arep the frame (max. length 32 byte) stored in xfifo can be polled repeatedly by the opposite station until the frame is acknowledged. ? extended transparent mode 0,1: xrep together with xtf- and xme-set (cmdr = 2a h ) the sacco repeatedly transmits the contents of the xfifo (132 bytes) fully transparent without hdlc-framing, i.e. without flag, crc-insertion, bit stuffing. the cyclical transmission continues until the command (cmdr:xres) is executed or the bit xrep is reset. the inter frame timefill pattern is issued afterwards. when resetting xrep, data transmission is stopped after the next xfifo- cycle is completed, the xres-command terminates data transmission immediately. bit 7 bit 0 rmc rhr arep/ xrep 0 xpd/ xtf xdd xme xres peb 20560 description of registers semiconductor group 5-95 1997-11-01 note: mode:cft must be set to 0 when using cyclic transmission. xpd/xtf transmit prepared data/transmit transparent frame. ? auto-mode: xpd prepares the transmission of an i-frame (prepared data) in auto-mode. the actual transmission starts, when the sacco receives an i-frame with poll-bit set and axh as the first data byte (pbc-command transmit prepared data). upon the reception of a different poll frame a response is generated automatically (rr-poll t rr-response, i-poll with first byte not axh t i-response). ? non-auto-mode, transparent mode 0,1: xtf the transmission of the xfifo contents is started, an opening flag sequence is automatically added. ? extended transparent mode 0,1: xtf the transmission of the xfifo contents is started, no opening flag sequence is added. xdd transmit direct data (auto-mode only!). prepares the transmission of an i-frame (direct data) in auto-mode. the actual transmission starts, when the sacco receives a rr-frame with poll-bit set. upon the reception of an i-frame with poll-bit set, an i-response is issued. xme transmit message end . a 1 indicate that the data block written last to the xfifo completes the actual frame. the sacco can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. xme is used only in combination with xpd/xtf or xdd. note: when using the dma-mode xme must not be used. xres transmit reset. the contents of the xfifo is deleted and idle is transmitted. this command can be used by the cpu to abort a frame currently in transmission. after setting xres a xpr-interrupt is generated in every case. peb 20560 description of registers semiconductor group 5-96 1997-11-01 5.1.2.7 mode register (mode) access: read/write reset value: 00 h mds10 mode select. the operating mode of the hdlc-controller is selected. 00auto-mode 01non-auto-mode 10transparent mode 11extended transparent mode adm address mode. the meaning of this bit varies depending on the selected operating mode: ? auto-mode / non-auto mode defines the length of the hdlc-address field. 08-bit address field, 116-bit address field. ? transparent mode 0no address recognition: transparent mode 0 1high byte address recognition: transparent mode 1 ? extended transparent mode 0receive data in ral1: extended transparent mode 0 1receive data in rfifo and ral1: extended transparent mode 1 note: in extended transparent mode 0 and 1 the bit mode:rac must be reset to enable fully transparent reception. cft continuous frame transmission. 1when cft is set the xpr-interrupt is generated immediately after the cpu accessible part of xfifo is copied into the transmitter section. 0otherwise the xpr-interrupt is delayed until the transmission is completed . rac receiver active. via rac the hdlc-receiver can be activated/deactivated. 0hdlc-receiver inactive 1hdlc-receiver active in extended transparent mode 0 and 1 rac must be reset (hdlc- receiver disabled) to enable fully transparent reception. tlp test loop. when set input and output of the hdlc-channel are internally connected. bit 7 bit 0 mds1 mds0 adm cft rac 0 0 tlp peb 20560 description of registers semiconductor group 5-97 1997-11-01 (transmitter channel a - receiver channel a transmitter channel b - receiver channel b) txda/b are active, rxda/b are disabled. 5.1.2.8 channel configuration register 1 (ccr1) access: read/write reset value: 00 h pu power-down mode. 0power-down (standby), the internal clock is switched off. nevertheless, register read/write access is possible. 1power-up (active). ods output driver select. defines the function of the transmit data pin (txda/b). 0txda/b-pin open drain output 1txda/b-pin push-pull output note: this bit has to be programmed for sidec0 even if sidec0 is not used. this bit is without function in sidec 1 3 itf inter frame time fill. determines the no data to send state of the transmit data pin (txda/b). 0continuous idle-sequences are output (11111111 bit pattern). 1continuous flag-sequences are output (01111110 bit pattern). cm2 clock rate. 0single rate data clock 1double rate data clock (iom-2) note: this bit has to be programmed for sidec0 even if sidec0 is not used. this bit is without function in sidec 1 3 bit 7 bit 0 pu 0 0 ods itf cm2 1 0 peb 20560 description of registers semiconductor group 5-98 1997-11-01 5.1.2.9 channel configuration register 2 (ccr2) access: read/write reset value: 00 h soc1 the function of the tsca/b-pin can be defined by programming soc1. point-to-point configuration: 0the tsca/b-output is activated during the transmission of a frame. 1the tsca/b-output is activated during the transmission of a frame and of inter frame timefill. xcs0, transmit/receive bit shift, bit 0. rcs0 together with the bits xcs2, xcs1 (rcs2, rcs1) in tsax (tsar) the bit shift relative to the frame synchronization signal of the transmit (receive) time-slot can be adjusted. a bit shift of 07 bits is programmable. ctsen clear to send enable bit 7 bit 0 soc1 0 xcs0 rcs0 0 ctsen rie 0 table 5-47 ctsen function 0 sidec channel operation with drdy signal according to the specification drdy = 1 go drdy = 0 stop 1 sidec is enabled; drdy is disconnected. collision detection is not applicable in this mode. peb 20560 description of registers semiconductor group 5-99 1997-11-01 figure 5-5 use of cts signal in sidec rie receive frame start enable. when set, the rfs-interrupt in register exir_a/b is enabled. 5.1.2.10 receive length check register (rlcr) access: write reset value: 0xxxxxxx h rc receive check enable. a 1 enables, a 0 disables the receive frame length feature. rl60 receive length. the maximum receive length after which data reception is suspended can be programmed in rl60. the maximum allowed receive frame length is (rl + 1) 32 bytes. a frame exceeding this length is treated as if it was aborted by the opposite station (rme-interrupt, rab-bit set). in this case the receive byte count (rbch, rbcl) is greater than the programmed receive length. 5.1.2.11 status register (star) access: read reset value: 48 h bit 7 bit 0 rc rl6 rl5 rl4 rl3 rl2 rl1 rl0 bit 7 bit 0 xdov xfw arep/ xrep rfr rli cec xac afi its10240 flip flop cts saccon sidec drdy 1 0 ctsen peb 20560 description of registers semiconductor group 5-100 1997-11-01 xdov transmit data overflow. a 1 indicates, that more than 32 bytes have been written into the xfifo. xfw xfifo write enable. a 1 indicates, that data can be written into the xfifo. note: xfw is only valid when cec = 0. arep/ auto repeat/transmission repeat. xrep read back value of the corresponding command bit cmdr:arep/xrep. rfr rfifo read enable. a 1 indicates, that valid data is in the rfifo and read access is enabled. rfr is set with the rme- or rpf-interrupt and reset when executing the rmc-command. rli receiver line inactive. neither flags as inter frame time fill nor frames are received via the receive line. note: significant in point-to-point configurations! cec command execution. when 0 no command is currently executed, the cmdr-register can be written to. when 1 a command (written previously to cmdr) is currently executed, no further command must temporarily be written to the cmdr-register. xac transmitter active. a 1 indicates, that the transmitter is currently active. afi additional frame indication. a 1 indicates, that one or more completely received frames or the last part of a frame are in the cpu inaccessible part of the rfifo. in combination with the bit star:rfr multiple frames can be read out of the rfifo without interrupt control. 5.1.2.12 receive status register (rsta) access: read reset value: xx h rsta always displays the momentary state of the receiver. because this state can differ from the last entry in the fifo it is reasonable to always use the status bytes in the fifo. vfr valid frame. indicates whether the received frame is valid (1) or not (0 invalid). bit 7 bit 0 vfr rdo crc rab ha1 ha0 c/r la peb 20560 description of registers semiconductor group 5-101 1997-11-01 a frame is invalid when C its length is not an integer multiple of 8 bits (n 8 bits), e.g. 25 bit, C its is to short, depending on the selected operation mode: auto-mode/non-auto mode (2-byte address field): 4 bytes auto-mode/non-auto mode (1-byte address field): 3 bytes transparent mode 1: 3 bytes transparent mode 0: 2 bytes C a frame was aborted (note: vfr can also be set when a frame was aborted) note: shorter frames are not reported. rdo receive data overflow. a 1 indicates, that a rfifo-overflow has occurred within the actual frame. crc crc-compare check. 0: crc check failed, received frame contains errors. 1: crc check o.k., received frame is error free. rab receive message aborted. when 1 the received frame was aborted from the transmitting station. according to the hdlc-protocol, this frame must be discarded by the cpu. ha10 high byte address compare. in operating modes which provide high byte address recognition, the sacco compares the high byte of a 2-byte address with the contents of two individual programmable registers (rah1, rah2) and the fixed values feh and fch (group address). depending on the result of the comparison, the following bit combinations are possible: 10rah1 has been recognized. 00rah2 has been recognized. 01group address has been recognized. note: if rah1, rah2 contain the identical value, the combination 00 will be omitted. ha10 is significant only in 2-byte address modes. c/r command/response; significant only, if 2-byte address mode has been selected. value of the c/r bit (bit of high address byte) in the received frame. la low byte address compare. the low byte address of a 2-byte address field or the single address byte of a 1-byte address field is compared with two programmable registers (ral1, ral2). depending on the result of the comparison la is set. 0ral2 has been recognized, 1ral1 has been recognized. in non-auto mode, according to the x.25 lap b-protocol, ral1/ral2 may be programmed to differ between command/response frames. peb 20560 description of registers semiconductor group 5-102 1997-11-01 note: the receive status byte is duplicated into the rfifo (clock mode 0-2) following the last byte of the corresponding frame. 5.1.2.13 receive hdlc-control register (rhcr) access: read reset value: xx h rhcr70 receive hdlc-control register. the contents of the rhcr depends on the selected operating mode. auto-mode (1- or 2-byte address field): i-frame compressed control field (bit 7-4: bit 7-4 of pbc-command, bit 3-0: bit 3-0 of hdlc-control field) else hdlc-control field note: rr-frames and i-frames with the first byte = axh (pbccommand transmit prepared data) are handled automatically and are not transferred to the cpu (no interrupt is issued). ? non-auto mode (1-byte address field): 2nd byte after flag ? non-auto mode (2-byte address field): 3rd byte after flag ? transparent mode 1: 3nd byte after flag ? transparent mode 0: 2nd byte after flag note: the value in rhcr corresponds to the last received frame. 5.1.2.14 transmit address byte 1 (xad1) access: write reset value: xx h xad1710 transmit address byte 1. the value stored in xad1 is included automatically as the address byte (high address byte in case of 2-byte address field) of all frames transmitted in auto mode. using a 2 byte address field, xad11 and xad10 have to be set to 0. bit 7 bit 0 rhcr7 rhcr6 rhcr5 rhcr4 rhcr3 rhcr2 rhcr1 rhcr0 bit 7 bit 0 xad17 xad16 xad15 xad14 xad13 xad12 xad11 xad10 peb 20560 description of registers semiconductor group 5-103 1997-11-01 5.1.2.15 transmit address byte 2 (xad2) access: write reset value: xx h xad2720 transmit address byte 2. the value stored in xad2 is included automatically as the low address byte of all frames transmitted in auto-mode (2-byte address field only). 5.1.2.16 receive address byte low register 1 (ral1) access: read/write reset value: xx h ral1710 receive address byte low register 1. the general function (read/write) and the meaning or contents of this register depends on the selected operating mode: ? auto-mode, non-auto mode (address recognition) - write only: compare value 1, address recognition (low byte in case of 2-byte address field). ? transparent mode 1 (high byte address recognition) - read only: ral1 contains the byte following the high byte of the address in the received frame (i.e. the second byte after the opening flag). ? transparent mode 0 (no address recognition) - read only: contains the first byte after the opening flag (first byte of the received frame). ? extended transparent mode 0,1 - read only: ral1 contains the actual data byte currently assembled at the rxd-pin by passing the hdlc-receiver (fully transparent reception without hdlc-framing). note: in auto-mode and non-auto mode the read back of the programmed value is inverted. bit 7 bit 0 xad27 xad26 xad25 xad24 xad23 xad22 xad21 xad20 bit 7 bit 0 ral17 ral16 ral15 ral14 ral13 ral12 ral11 ral10 peb 20560 description of registers semiconductor group 5-104 1997-11-01 5.1.2.17 receive address byte low register 2 (ral2) access: write reset value: xx h ral2720 receive address byte low register 1. ? auto-mode, non-auto mode (address recognition): compare value 2, address recognition (low byte in case of 2-byte address field). note: normally used for broadcast address. 5.1.2.18 receive address byte high register 1 (rah1) access: write reset value: xx h rah1712 receiver address byte high register 1. ? auto-mode, non-auto mode transparent mode 1, (2-byte address field). compare value 1, high byte address recognition. note: when a 1-byte address field is used in non-auto or auto-mode, rah1 must be set to 00 h . 5.1.2.19 receive address byte high register 2 (rah2) access: write reset value: xx h rah2722 receiver address byte high register 2. ? auto-mode, non-auto mode transparent mode 1, (2-byte address field). compare value 2, high byte address recognition. note: when a 1-byte address field is used in non-auto or auto-mode, rah2 must be set to 00 h . bit 7 bit 0 ral27 ral26 ral25 ral24 ral23 ral22 ral21 ral20 bit 7 bit 0 rah17 rah16 rah15 rah14 rah13 rah12 0 0 bit 7 bit 0 rah27 rah26 rah25 rah24 rah23 rah22 0 0 peb 20560 description of registers semiconductor group 5-105 1997-11-01 5.1.2.20 receive byte count low (rbcl) access: read reset value: 00 h rbc70 receive byte count. together with rbch (bits rbc11-rbc8), the length of the actual received frame (04095 bytes) can be determined. these registers must be read by the cpu following a rme interrupt. 5.1.2.21 receive byte count high (rbch) access: read ov counter overflow. a 1 indicates that more than 4095 bytes were received. the received frame exceeded the byte count in rbc11rbc0. rbc118 receive byte count high. together with rbcl (bits rbc7rbc0) the length of the received frame can be determined. 5.1.2.22 time-slot assignment register transmit (tsax) access: write reset value: xx h tsnx50 time-slot number transmit. selects one of up to 64 time-slots (00 h -3f h ) in which data is transmitted. the number of bits per time-slot is programmable in register xccr. xcs21 transmit bit shift bit2-1. together with xcs0 in register ccr2 the transmit bit shift can be adjusted. bit 7 bit 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 bit 7 bit 0 0 0 0 ov rbc11 rbc10 rbc9 rbc8 bit 7 bit 0 tsnx5 tsnx4 tsnx3 tsnx2 tsnx1 tsnx0 xcs2 xcs1 peb 20560 description of registers semiconductor group 5-106 1997-11-01 5.1.2.23 time-slot assignment register receive (tsar) access: write reset value: xx h tsnr50 time-slot number receive. selects one of up to 64 time-slots (00 h - 3f h ) in which data is received. the number of bits per time-slot is programmable in register rccr. rcs21 receive bit shift bit2-1. together with rcs0 in register ccr2 the transmit bit shift can be adjusted. 5.1.2.24 transmit channel capacity register (xccr) access: write reset value: 00 h xbc70 transmit bit count. defines the number of bits to be transmitted in a time-slot in clock mode 2 (number of bits per time-slot = xbc + 1 (1256 bits/time-slot)). note: in extended transparent mode the width of the time-slot has to be n 8 bits. 5.1.2.25 receive channel capacity register (rccr) access: write reset value: 00 h rbc70 receive bit count. defines the number of bits to be received in a time-slot. number of bits per time-slot = rbc + 1 (1256 bits/time-slot). note: in extended transparent mode the width of the time-slot has to be n 8 bits. bit 7 bit 0 tsnr5 tsnr4 tsnr3 tsnr2 tsnr1 tsnr0 rcs2 rcs1 bit 7 bit 0 xbc7 xbc6 xbc5 xbc4 xbc3 xbc2 xbc1 xbc0 bit 7 bit 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 peb 20560 description of registers semiconductor group 5-107 1997-11-01 5.1.2.26 version status register (vstr) access: read vn30 sacco version number. 82 h sidec in doc v1.1. 83 h sidec in doc v2.1. bit 7 bit 0 1000vn3vn2vn1vn0 peb 20560 applications semiconductor group 6-1 1997-11-01 6 applications as the doc is a powerful device it is possible to show only a few of the possible system configurations. because the dsp is connected to one or to two cfi ports, which can be programmed to operate in iom-2 or in pcm mode, and the user also can program the number of b-channels the dsp is supposed to use (n 4 time-slots, n = 0 to 16), it is difficult to count how many iom-2 ports are fully or partly usable for layer-1 ic connection C this strongly depends on the specific application. 6.1 doc in a small pbx the application is characterized by a high number of iom-2 channels and a low number of time-slots at the pcm highway. 6.1.1 small pbx with 2.048 mbit/s data rate in this mode, the doc provides: ? 6 fully usable iom-2 (gci) interfaces with 48 iom-2 subframes (6 8) and thus it can control up to 48 isdn or 96 analogue subscribers. ? 2 partly usable iom-2 interfaces, as the two dsp ports are connected to them. ? 4 pcm highways with 128 timeslots, as the two elics must be connected together. peb 20560 applications semiconductor group 6-2 1997-11-01 figure 6-1 doc in a small pbx with 2.048 mbit/s data rate note: sacco-b1 can be used as signaling controller but not as a stand alone controller. its10108 sacco-a0 elic r -0 sacco-b0 0 1 2 3 0 1 2 3 sacco-a1 sacco-b1 33 elic 2 1 0 -1 r 2 1 0 dsp signaling r iom -2 interfaces 6 x 32 ts = 192 ts doc pcm highways 2.048 mbit/s 4 x 32 ts = 128 ts 2.048 mbit/s 2 x 32 ts peb 20560 applications semiconductor group 6-3 1997-11-01 6.1.2 small pbx with 4.096 mbit/s data rate in this mode, the doc provides: ? 2 fully usable iom-2 interfaces with 32 iom-2 subframes (2 16) and ? 2 partly usable iom-2 interfaces with 16 iom-2 subframes (2 8) and thus ? control of up to 48 isdn or 96 analogue subscribers. ? 2 pcm highways with 128 timeslots, as the two elics must be connected together. figure 6-2 doc in a small pbx with 4.096 mbit/s data rate its10109 sacco-a0 elic r -0 sacco-b0 0 1 2 3 0 1 2 3 sacco-a1 sacco-b1 33 elic 2 1 0 -1 r 2 1 0 dsp signaling r iom -2 interfaces 2 x 32 dps ts doc pcm highways 4.096 mbit/s 2 x 64 ts = 128 ts 4.096 mbit/s 2 x 32 ts 4 x 64 ts minus = 192 ts peb 20560 applications semiconductor group 6-4 1997-11-01 6.2 doc on line card this mode is characterized by a low number of supported iom-2 subframes and a high number of needed time-slots at the pcm highway. as the doc is complex it is possible to show only a few of all possible configurations. 6.2.1 line card with 2.048 and 4.096 mbit/s data rates in this mode, the doc provides: ? 2 fully usable iom-2 interfaces with 16 iom-2 subframes (2 8) and ? 2 limited iom-2 interfaces, as two dsp ports are connected. ? 4 pcm highways with 256 time-slots (4 64). figure 6-3 doc on line card with 2.048 and 4.096 mbit/s data rates note: sacco-b1 can be used also as a stand alone controller with all support lines as the elic1 iom-2 ports are not used in this mode. its10110 sacco-a0 elic r -0 sacco-b0 0 1 2 3 0 1 2 3 sacco-a1 sacco-b1 33 elic 2 1 0 -1 r 2 1 0 dsp signaling r iom -2 interfaces 2 x 32 ts = 64 ts doc pcm highways at 2.048 mbit/s 4 x 64 ts = 256 ts at 4.096 mbit/s stand alone controller 2 x 32 ts peb 20560 applications semiconductor group 6-5 1997-11-01 6.2.2 line card with 4.096 and 8.192 mbit/s data rates in this mode, the doc provides: ? 2 partly usable iom-2 interfaces with 16 iom-2 subframes (2 16 minus 2 8) as the two dsp ports are connected. ? 2 pcm highways with 256 time-slots (2 128). note: sacco-b1 can be used also as a stand alone controller with all support lines as the elic1 iom-2 ports are not used in this mode. figure 6-4 doc on line card with 4.096 and 8.192 mbit/s data rates its10111 sacco-a0 elic r -0 sacco-b0 0 1 2 3 0 1 2 3 sacco-a1 sacco-b1 33 elic 2 1 0 -1 r 2 1 0 dsp signaling r iom -2 interfaces 2 x 32 ts = 64 ts doc pcm highways 4.096 mbit/s 2 x 128 ts = 256 ts at 8.192 mbit/s 2 x 32 ts 2 x 64 ts minus stand alone controller peb 20560 applications semiconductor group 6-6 1997-11-01 6.3 clock generation 6.3.1 pbx with one doc an external reference clock is selected, e.g. 1.536 mhz from quat-s in lt-t mode. figure 6-5 clock generation in a pbx with one doc the quat-s provides a synchronous 1.536 mhz clock (adaptive timing recovery). a synchronized doc generates pfs, pdc2, pdc4, pdc8, fsc and dcl. the pfs length must be at least 3 dcl period long when the pfs is used for iom-2 synchronization (instead of fsc). a short pulse would be interpreted as a sync. pulse for multiframe synchronization. its10112 doc peb 20560 pfs pdc2 pdc4 pdc8 refclc quat lt-s te s-interface 192 khz lt-t central office master r iom -2 interface clk7 7.68 mhz dcl 4.096 mhz fsc 8 khz t-interface 192 khz xclk 1.536 mhz -s r quat r -s peb 20560 applications semiconductor group 6-7 1997-11-01 6.3.2 pbx with multiple docs pbxs may use multiple line cards with one doc on each line card. figure 6-6 clock synchronization in a pbx with multiple docs the following initialization sequence is recommended after reset: 1. one doc, selected by the m p as system master, generates free running master clocks pfs and pdc2/4/8 used for fsc and dcl generation on all docs/line cards. the system master is selected by the m p via a line card code (or doc code). 2. one doc, connected to the central office is selected by the m p as clock master. this doc synchronizes to the central office clock via its trunk line (refer to the figure 6-5 ) and generates a reference clock refclk for system master resynchronization. refclk = xclk divided by 4 or 3 or it equals xclk. doc peb 20560 board code local network pdc2, pdc4, pdc8 pfs refclk pcm r sicofi -4 octat -p r iec-4 dfe & afe line-card 0 u k pn u s0/t t/r line-card n k u s0/t pn u t/r r dfe & afe iec-4 octat -p r sicofi -4 peb 20560 doc - priority - local network - clocks - pcm highway backplane subscribers mpu ram mpu ram pfs board code local network pdc2, pdc4, pdc8 refclk pcm backplane its10113 quat r -s quat -s r peb 20560 applications semiconductor group 6-8 1997-11-01 the clock master is selected by the m p via the integrated local network controller (lnc). 3. the system master synchronizes its master clocks pfs and pdc2/4/8 to the refclk. 4. all other docs resynchronize fsc and dcl (shift by a delta) to the system master. the doc hardware will be optimized so that the phase shift will be minimal and constant for all docs. 6.4 signaling with sidec the four independent communication channels of the sidec can be used either for data communication with terminals (or pcs) or in connection with quat-s for communication to the central office. if the quat-s is used for lt-t applications, the sidec must be assigned with all involved channels to one iom-2 interface. see figure 6-7 . the pin drdy conveys control information synchronously to the d-channel time-slots to control the sidec. refer also to figure 2-22 and figure 2-23 . figure 6-7 quat-s in lt-t mode with sidec for four-channel trunk applications its10114 0 3 peb 2084 t-interfaces r iom -2 elic sidec drdy drdy "0" = stop "1" = go doc m p quat r -s peb 20560 applications semiconductor group 6-9 1997-11-01 6.5 local network controller (sacco-b1 as lnc) the lnc can be used: ? for inter doc communication when multiple docs are cascaded (i.e. for doc selection to generate refclk) ? for signaling, if externally connected to iom-2 or pcm interfaces ? as a general purpose hdlc controller (up to 8.192 mbit/s). the max. length of the transmit line may reach up to 2 m. the high speed data rate may be handled by an external dma controller. 6.6 uart applications the uart can be used for: ? system tests in the development phase ? field tests ? program download (i.e. via a v.24 interface) 6.7 iom ? -2 channel indication signal (chi) the chi signal in addition to the iom-2 signals can be used for indication to any connected layer-1 ic that the data sent downstream is not iom-2 compatible data. by the use of chi signal a proprietary data channel can be implemented. 6.8 use of fscd in case of connecting 2 octat-p or four quat-s to a 4.096 mbit/s iom-2 interface (extended iom-2 specification) a second fsc, delayed by 62.5 m s, is provided. it synchronizes the layer-1 ics connected to the time-slots 32 to 63. layer-1 ics connected to the time-slots 0 to 31 use the standard fsc signal. 6.9 watch-dog activation 1. activation (a disactivation by software is not possible after its activation) 2. triggering both watch-dog registers by software 3. flag reset indication if software triggering fails; however doc remains unaffected 6.10 tone and voice processing the integrated dsp (oak) is supposed to execute routines for tone and voice processing such as: ? tone generation and recognition ? dtmf transmitter and receiver ? music on hold ? conferencing ? voice mail and voice recording peb 20560 applications semiconductor group 6-10 1997-11-01 (a-/ m -law coding and decoding is performed by firmware, independently of the dsp) 1) country specific number 2) user specific 3) modem for exceptional use as not all dsp routines are running at the same time and the integrated dsp provides 40 mips, additional dsp routines can be implemented by the user. for monitoring and optimizing the dsp load, the programmer can use the statistics register. siemens also provides a pc based expert system for fast and correct doc initialization, refer to doc configurator, chapter 9.6 . table 6-1 an example for required dsp performance in a comfort pbx with 30 subscribers performance dsp functionality mips per channel channels/ operation mips total dtmf generator 0.37 4 1.48 dtmf receiver 1.8 8 14.4 tone generator 0.2 4 1) 0.8 tone receiver (from co) 0.4 4 1.6 music on hold 0.2 2 2) 0.4 conferencing 0.7 4 5 2.8 modem v.21 (300 baud) 3) 4.0 1 4.0 operating system 2.0 2.0 27 mips peb 20560 applications semiconductor group 6-11 1997-11-01 6.11 dsp frequency recommendation depending on the speed (price) of the connected external memory (sram) the following maximal dsp frequency and thus dsp performance (number of mips) is possible; estimation: 1) sram access time is the time from valid read address to the valid data. 2) the doc provides 20.48 mhz 3) the doc provides 30.72 mhz 4) the highest dsp frequency of 40 mhz (and all above recommended max. dsp frequencies can only be confirmed after doc characterization). refer also to external data read access timing, table 7-24 . sram access time 1 ) max. dsp frequency note 33.5 ns 20 mhz doc requires an ext. quartz 2) 22 ns 26 mhz doc requires an ext. quartz 16.8 ns 30 mhz doc requires an ext. quartz 3) 13.8 ns 33 mhz 3) 10.5 ns 37 mhz doc requires an ext. quartz 8.5 ns 40 mhz 4) doc requires an ext. quartz peb 20560 electrical characteristics semiconductor group 7-1 1997-11-01 7 electrical characteristics 7.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 operating range note: in the operating range, the functions given in the circuit description are fulfilled table 7-1 parameter symbol limit values unit ambient temperature under bias peb pef t a t a 0 to 70 - 40 to 85 c c storage temperature t stg - 65 to 125 c ic supply voltage v dd - 0.4 to 4.6 v protection supply voltage v ddp - 0.5 to 5.5 v voltage on any pin with respect to ground v s - 0.4 to v ddp + 0.4 v maximum current on all lines connected to the backplane when the doc is without power supply; at 5.5 v external signal level i max 2.3 ma table 7-2 parameter symbol limit values unit test condition min. max. ambient temperature t a 070 c supply voltage v dd 3.13 3.6 v protection supply voltage v ddp 4.5 5.5 v v ss 00v peb 20560 electrical characteristics semiconductor group 7-2 1997-11-01 7.3 dc characteristics note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. 1) apply to the next pins: txdb0, dd0, dd1, dd2, dd3, dd4/txdb1, dd5/tscb1 , dd6/drqtb1, dd7/ drqrb1, txd0, txd1, txd2, txd3. 2) apply to all the i/o and o pins that do not appear in the list in note 1) , except clk40-xo. table 7-3 parameter symbol limit values unit notes min. max. input low voltage v il - 0.4 0.8 v input high voltage v ih 2.0 v ddp + 0.4 v output low voltage v ol 0.45 v i ol = 7 ma 1) i ol = 2 ma 2) output high voltage v oh 2.4 v i oh = C 1.0 ma typical power supply current i cc (av) 115 ma v dd = 3.3 v, t a = 25 c: pdc = 8 mhz hdc = 4 mhz dsp clock = 30 mhz input leakage current i il 1 m a v dd = 3.3 v, gnd = 0 v; all other pins are floating; v in = 0 v, v ddp + 0.4 output leakage current i oz 1 m a v dd = 3.3 v, gnd = 0 v; v out = 0 v, v ddp + 0.4 peb 20560 electrical characteristics semiconductor group 7-3 1997-11-01 7.4 capacitances 7.5 strap pins pull-up resistors specification the strap input pins are sampled during reset, and determine some modes of the doc. the strap inputs are: cdb0/boot, cdb1/dbg, cdb2/rom, cdb4/urst and cdb12/ seibdis. when a strap input pin is not driven externally during reset, it is driven internally by an internal pull-down. if a fixed external pull-up is applied on a strap, a pull-up resistor of 5 k w is required. the required precision of the resistor is 10% . 7.6 40 mhz external crystal . c ld = 2 c l - c clk40-x(1 or 0) note: other external crystals may be used (up to 40 mhz). however, the external circuitry must be changed accordingly. table 7-4 parameter symbol limit values unit notes min. max. clock input capacitance c xin pf f c = 1 mhz the pins, which are not under test, are connected to gnd clock output capacitance c xout pf input capacitance c in pf output capacitance c out pf table 7-5 parameter symbol limit values unit notes min. max. clock input capacitance c lk40-xi 7pf clock output capacitance c lk40-xo 7pf motional capacitance c 1 20 ff shunt c o 5pf load c l 20 pf resonance resistor r 1 50 w peb 20560 electrical characteristics semiconductor group 7-4 1997-11-01 figure 7-1 7.7 general recommendations and prohibitions 1. any doc input pin should not left disconnected, even if its unused. clk-40xi, especially, should be permanently driven by v ss , it is unused. 7.8 ac characteristics ambient temperature under bias range, v dd = 3.13-3.6 v. inputs are driven to 2.4 v for a logic 1 and to 0.4 v for logic 0. timing measurements are made at 2.0 v for a logic 1 and at 0.8 v for a logic 0. the ac-testing input/output waveforms are shown below. figure 7-2 i/o-wave form for ac-test its10115 c ld ld c clk40-xi clk40-x0 40 mhz 100 ppm its10116 = 50 pf l c test under device 2.4 v 0.4 v 2.0 v 0.8 v 2.0 v 0.8 v test points peb 20560 electrical characteristics semiconductor group 7-5 1997-11-01 7.9 microprocessor interface timing figure 7-3 address timing table 7-6 bus interface timing parameter symbol limit values unit min. max. rd -pulse width t rr 80 ns rd -control interval t ri 50 ns data output delay from rd t rd 65 ns data float delay from rd t df 525ns dma-request delay t drh 75 ns wr -pulse width t ww 30 ns wr -control interval t wi 40 ns data set-up time to wr t dw 30 ns data hold time from wr t wd 15 ns ale-pulse width t aa 15 ns address set-up time to ale t al 10 ns address hold time from ale t la 8ns ale set-up time to wr , rd t al s 8ns cs set-up time to wr , rd t cs 5ns cs hold-time from wr , rd t sc 5ns itt10117 ad7 - ad0 al t a9 - a8 ale cs wr rd t aa t la als t t cs t sc peb 20560 electrical characteristics semiconductor group 7-6 1997-11-01 figure 7-4 data timing itt10118 cs x rd ad0 - ad7 dd7/drqrb1 drqrb0/ (case n = 4, 8, 16) (case n = 32, dd7/drqrb1 drqrb0/ read cycle 31) rd t t df t rr ri t t drh drh t m p read cycle dd6/drqtb1 (write cycle n - 1) p write cycle drqtb0/ ad0 - ad7 cs x wr m t dw t drh t ww t wd t w data data peb 20560 electrical characteristics semiconductor group 7-7 1997-11-01 table 7-7 siemens/intel interrupt timing parameter symbol limit values unit min. max. iack pulse width t ii 70 ns iack control interval t ici 40 ns ireq reset after last iack inactive t iack-int 200 ns slave address (ie0, ie1) setup time t sai 5ns slave address (ie0, ie1) hold time t isa 0ns interrupt vector (d7-d0) valid after iack active t ivv 50 ns interrupt vector (d7-d0) valid after iack inactive t ivh 540ns ie0 low after ie1 low t ie10l 20 ns ie0 high after ie1 high t ie10h 20 ns ie0 low after ireq active t irieol 10 ns ireq inactive after ie1 low t disint 25 ns ireq reactivated after ie1 high t ie1h-intv 25 ns ie0 high after ireq reset t int-ie0h 10 ns peb 20560 electrical characteristics semiconductor group 7-8 1997-11-01 figure 7-5 siemens/intel interrupt timing (slave mode) note: 1) the timing is valid for active-high push-pull signal. the timing for active-low push-pull signal is the same. in the case of open drain output, reset time ( t iack-int ) depends on external devices. 2) t iack-int is valid only for fsc and rtc interrupts. the other interrupts are reset only by reading/writing from/to the appropriate register, in the interrupt source module (see figure 7-9 ). 3) wr , rd and cs must not be activated during iack activation. itt10119 ireq note 1, 2 iack ie 1, 0 d7 - d0 wr, rd, cs note 3 int vector slave address ii t ici t iack-int t ic t t sai isa t t ivh t ivv float peb 20560 electrical characteristics semiconductor group 7-9 1997-11-01 figure 7-6 siemens/intel interrupt timing (daisy chaining) note: 1) the timing is valid for active-high push-pull signal. the timing for active-low push-pull signal is the same. in the case of an open drain output, reset times ( t iack-int , t disint ) depend on external devices. 2) the timing for ireq, iack and d7-d0 is similar to slave mode. 3) t iack-int is valid only for fsc and rtc interrupts. the other interrupts are reset only by reading/writing from/to the appropriate register, in the interrupt source module (see figure 7-9 ). itt10120 ireq note 1 ie1 ie0 iack disint t ie1h-intv t t ie10l ie10h t irie0l t int-ie0h t t iack-int note 2, 3 peb 20560 electrical characteristics semiconductor group 7-10 1997-11-01 table 7-8 motorola interrupt timing parameter symbol limit values unit min. max. iack pulse width t ii 85 ns iack control interval t ici 40 ns ireq reset after last iack inactive t iack-int 200 ns slave address (ie0, ie1) setup time t sai 5ns slave address (ie0, ie1) hold time t isa 0ns interrupt vector (d7-d0) valid after iack active t ivv 75 ns interrupt vector (d7-d0) valid after iack inactive t ivh 540ns ie0 low after ie1 low t ie10l 20 ns ie0 high after ie1 high t ie10h 20 ns ie0 low after ireq active t irieol 10 ns ireq inactive after ie1 low t disint 25 ns ireq reactivated after ie1 high t ie1h-intv 25 ns ie0 high after ireq reset t int-ie0h 10 ns peb 20560 electrical characteristics semiconductor group 7-11 1997-11-01 : figure 7-7 motorola interrupt timing (slave mode) note: 1) the timing is valid for active-high push-pull signal. timing for active-low push- pull signal is the same. in the case of open drain output, reset time ( t iack-int ) depends on external devices. 2) t iack-int is valid only for fsc and rtc interrupts. the other interrupts are reset only by reading/writing from/to the appropriate register, in the interrupt source module (see figure 7-9 ). 3) wr , rd and cs must not be activated during iack activation. itt10121 ireq note 1 iack ie 1, 0 d7 - d0 wr, rd, cs note 3 int vector slave address iack-int t ici t t sa isa t t ivh t ivv float t ii float peb 20560 electrical characteristics semiconductor group 7-12 1997-11-01 . figure 7-8 motorola interrupt timing (daisy chaining) note: 1) the timing is valid for active-high push-pull signal. the timing for active-low push-pull signal is the same. in the case of an open drain output, reset times ( t iack-int , t disint ) depend on external devices. 2) the timing for ireq, iack and d7-d0 is similar to slave mode. 3) t iack-int is valid only for fsc and rtc interrupts. the other interrupts are reset only by reading/writing from/to the appropriate register, in the interrupt source module (see figure 7-9 ). table 7-9 interrupt timing parameter symbol limit values unit min. max. interrupt inactivation delay t ai 200 ns itt10122 ireq note 1 ie1 ie0 iack disint t ie1h-intv t t ie10l ie10h t irie0l t int-ie1h t t iack-int note 2 peb 20560 electrical characteristics semiconductor group 7-13 1997-11-01 figure 7-9 interrupt inactivation from wr , rd note: 1) timing valid for active-high push-pull signal. timing for active-low push-pull signal is the same. in the case of open-drain output, t ai depends on external devices. 2) ireq output signal may be inactivate by read instruction from the appropriate registers in elic0/elic1, sidec 0-4 and the gpio or write instruction to the appropriate registers in the uart and in the oak mail-box. 7.9.1 pcm interface timing table 7-10 pdc and pfs timing in master mode parameter symbol limit values unit notes min. max. clk16 clock period t cp16 see table 7-27 clk16 clock period high t cph16 clk16 clock period low t cpl16 itt10123 ai t ireq note 1 rd, wr peb 20560 electrical characteristics semiconductor group 7-14 1997-11-01 1) when using one doc as a master of other slave doc, the c load of pfs must not be greater then the c load of pdc 2/4/8 (especially pdc8) in more then 25% pdc8 output clock period t ocp8 120 ns clk16 = 16.384 mhz, c load = 50 pf 1) pdc8 output clock period low t ocpl8 45 ns pdc8 output clock period high t ocph8 45 ns pdc4 output clock period t ocp4 240 ns pdc4 output clock period low t ocpl4 105 ns pdc4 output clock period high t ocph4 105 ns pdc2 output clock period t ocp2 480 ns pdc2 output clock period low t ocpl2 225 ns pdc2 output clock period high t ocph2 225 ns clock delay clk16-pdc8 t cd16pd8 623ns clock delay clk16-pdc4 t cd16pd4 726ns clock delay clk16-pdc2 t cd16pd2 829ns clock delay clk16-pfs t cd16pf 13 43 ns clock delay pdc8-pfs t cdp8pf 20 ns clock delay pdc4-pfs t cdp4pf 18 ns clock delay pdc2-pfs t cdp2pf 15 ns table 7-10 pdc and pfs timing in master mode parameter symbol limit values unit notes min. max. peb 20560 electrical characteristics semiconductor group 7-15 1997-11-01 figure 7-10 pdc and pfs timing in master mode (pdc & pfs are outputs) note: when in master mode, the pulse width of pfs (pfs period high ) is 4 pdc2 cycles = 8 pdc4 cycles = 16 pdc8 cycles . table 7-11 pcm-interface timing in master mode parameter symbol limit values unit notes min. max. clock period t cp 1) see table 7-10 clock period low t cpl 2) clock period high t cph 3) frame delay from pdc t fpd 4) serial data input set-up time t s 37 ns pcm data frequency > 4096 kbit/s serial data input hold time t h 25 ns itt10124 clk16 (ccselo:ms = 0) pdc 8 (ccselo:ms = 0) pdc 4 (ccselo:ms = 0) pdc 2 (ccselo:ms = 0) pfs note 1 cp16 t cph16 t cph16 t t cd16pd8 t ocp8 t ocph8 t ocpl8 cd16pd8 t cd16pd4 t ocp4 t ocpl4 t t cd16pd4 ocph4 t cd16pd2 t cd16pd2 t ocp2 t ocpl2 t ocph2 t cd16pf t cd16pf t cdp2pf t cdp4pf t cdp8pf t cdp2pf cdp4pf cdp8pf t t t peb 20560 electrical characteristics semiconductor group 7-16 1997-11-01 1) for more details about t cp , see t ocp8 , t ocp4 and t ocp2 , in table 7-10 . 2) for more details about t cpl , see t ocpl8 , t ocpl4 and t ocpl2 , in table 7-10 . 3) for more details about t cph , see t ocph8 , t ocph4 and t ocph2 , in table 7-10 . 4) the c load of pfs must not be greater then the c load of pdc2/4/8 (especially pdc8) in more then 25%. for more details about t fpd , see t cdp8pf , t cdp4pf and t cdp2pf , in table 7-10 serial data input set-up time t s 50 ns pcm data frequency < 4096 kbit/s serial data input hold time t h 45 ns pcm-serial data output delay t d 15 51 ns tri-state control delay t t 550ns table 7-11 pcm-interface timing in master mode (contd) parameter symbol limit values unit notes min. max. peb 20560 electrical characteristics semiconductor group 7-17 1997-11-01 figure 7-11 pcm-interface timing in master mode itt10125 pdc 2/4/8 (ccselo:ms = '1') (pmod:psm = 0) ccselo:ms = '1') pfs txd (pcsr:ure = 1) tsc (pcsr:ure = 1) 1st bit of frame 2nd bit of frame 3rd bit of frame 1st bit of frame 1st bit of frame rxd (pcsr:dre = 0) txd (pcsr:ure = 0) 1st bit of frame 1st bit of frame tsc (pcsr:ure = 0) rxd (pcsr:dre = 1) 1st bit of frame txd (pcsr:ure = 1) 1st bit of frame tsc (pcsr:ure = 1) 1st bit of frame 1st bit of frame rxd (pcsr:dre = 0) 1st bit of frame txd (pcsr:ure = 0) tsc (pcsr:ure = 0) 1st bit of frame 1st bit of frame rxd (pcsr:dre = 1) pmod:pcr = 1 t cp t cph cpl t t fpd t t d t h t s t t d t t h t t s t d t t t t d t s t h t s t h t pmod:pcr = 0 t fpd peb 20560 electrical characteristics semiconductor group 7-18 1997-11-01 table 7-12 pcm interface timing in slave mode parameter symbol limit values unit notes min. max. clock period t cp 240 ns clock frequency < 4096 khz clock period low t cpl 50 ns clock period high t cph 60 ns clock period t cp 120 ns clock frequency > 4096 khz clock period low t cpl 30 ns clock period high t cph 30 ns frame set-up time to clock t fs 36 ns frame hold time from clock t fh 58 ns serial data input set-up time t s 16 ns pcm data frequency > 4096 kbit/s serial data hold time t h 44 ns serial data input set-up time t s 29 ns pcm data frequency < 4096 kbit/s serial data hold time t h 64 ns tri-state control delay t t 15 60 ns pcm - serial data output delay t d 18 56 ns pcm data frequency > 4096 kbit/s pcm - serial data output delay t d 22 66 ns pcm data frequency < 4096 kbit/s peb 20560 electrical characteristics semiconductor group 7-19 1997-11-01 figure 7-12 pcm-interface timing in slave mode itt10126 pdc 2/4/8 (ccselo:ms = '0') (ccselo:ms = '0') pfs (pmod:psm = 0) (pmod:psm = 1) (ccselo:ms = '0') pfs txd (pcsr:ure = 1) tsc (pcsr:ure = 1) 1st bit of frame 2nd bit of frame 3rd bit of frame 1st bit of frame rxd (pcsr:dre = 0) txd (pcsr:ure = 0) 1st bit of frame 1st bit of frame tsc (pcsr:ure = 0) rxd (pcsr:dre = 1) 1st bit of frame txd (pcsr:ure = 1) 1st bit of frame tsc (pcsr:ure = 1) 1st bit of frame 1st bit of frame rxd (pcsr:dre = 0) 1st bit of frame txd (pcsr:ure = 0) tsc (pcsr:ure = 0) 1st bit of frame 1st bit of frame rxd (pcsr:dre = 1) pmod:pcr = 1 fs t t cp t cph cpl t fs t t fh t fh fs t t fh fs t t fh t t d t h t s t t d t t h t t s t d t t t t d t s t h t s t h t pmod:pcr = 0 note 1 1st bit of frame peb 20560 electrical characteristics semiconductor group 7-20 1997-11-01 7.9.2 iom ? -2 interface timing table 7-13 iom ? -2 interface clocks timing when fsc and dcl are driven by elic0 and the doc is in slave mode parameter symbol limit values unit notes min. max. frame set-up time to clock t fs ns see table 7-12 frame hold time from clock t fh ns data clock delay when driven by elic0 t dcde ns peb 20560 electrical characteristics semiconductor group 7-21 1997-11-01 figure 7-13 iom ? -2 interface clocks timing when fsc and dcl are driven by elic0 and the doc is in slave mode itt10127 (elic0/1:css = 0; pdc 2/4/8 elic0/1:cmd1:css = 0; (elic0/1:pmod:psm = 0; pfs ccsel:ms = 0) ccsel:ms = 0) elic0/1:cmd1;css = 0; (elic0/1:pmod:psm = 1; pfs elic0:cmd2:coc = 1) (elic0:cmd1 = 1000xx dcl (elic0:fc(2:0) = 011) fsc (elic0:cmd1 = 0101xx elic0:cmd2:coc = 0) dcl (elic0:cmd2:fc(2:0) = 011) fsc dcl elic0:cmd2:coc = 0) (elic0:cmd1 = 0010xx (elic0:cmd2:fc(2:0) = 011) fsc ccsel:ms = 0) fs t fs t t fh t fh fs t fh t fs t t fh t dcde dcde t dcde t dcde t dcde dcde t t dcde t dcde t dcde t dcde t dcde t dcde t prescalor divisor = 2 prescalor divisor = 1.5 prescalor divisor = 1 h ; h ; h ; peb 20560 electrical characteristics semiconductor group 7-22 1997-11-01 figure 7-14 iom ? -2 interface clocks timing when fsc and dcl are driven di- rectly by pdc4/8 and pfs, and the doc is in slave mode table 7-14 iom ? -2 interface clocks timing when fsc and dcl are driven directly by pdc4/8 and pfs, and the doc is in slave mode parameter symbol limit values unit notes min. max. frame set-up time to clock t fs ns see table 7-12 frame hold time from clock t fh ns data clock delay when driven directly by pdc 4/8 t dcdp 31 ns fsc delay from pfs t fscd 30 ns itt10128 (ccsel0:ms = 0) pdc 4/8 elic0/1:pmod:psm = 0) (ccsel0:ms = 0; pfs (ccsel1:fscs = 0; elic0:cmd1:css = 1) dcl elic0:cmd1:css = 1) (ccsel1:fscs = 0; fsc fh t t fs t fs t fh dcdp t dcdp t fscd t fscd t fscd t peb 20560 electrical characteristics semiconductor group 7-23 1997-11-01 table 7-15 iom ? -2 interface clocks timing when fsc and dcl are driven directly by pdc4/8 and pfs, and the doc is in master mode (pdc and pfs are generated by internal clocks generator) parameter symbol limit values unit notes min. max. clk16 clock period t cp see table 7-27 clk16 clock period high t cph16 clk16 clock period low t cpl16 clock delay clk16 to fsc t cd16fs 13 46 ns clock delay clk16 to dcl t cd16dc 834 clock delay dclto fsc t cddcfs 733 when dcl (output) is driven internally by pdc8 generated dcl clock period t gdcp 122 ns ccsel1 = xxxxx000; ccsel0: ms = 1; elic0:cmd1: css = 1 generated clock period high t gdcph 50 ns generated clock period low t gdcpl 50 ns when dcl (output) is driven internally by pdc4 generated dcl clock period t gdcp 244 ns ccsel1 = xxxxx010; ccsel0: ms = 1; elic0:cmd1: css = 1 generated clock period high t gdcph 105 ns generated clock period low t gdcpl 105 ns peb 20560 electrical characteristics semiconductor group 7-24 1997-11-01 figure 7-15 iom ? -2 interface clocks timing when fsc and dcl are driven di- rectly by pdc4/8 and pfs, and the doc is in master mode (pdc and pfs are generated by internal clocks generator) note: when fsc and dcl are driven by pfs and pdc4/8, which are generated by internal clocks generator, the pulse width of fsc (fsc period high) is 8 dcl cycles, when dcl is driven by pdc4, or 16 dcl cycles, when dcl is driven by pdc8. table 7-16 iom ? -2 interface timing parameter symbol limit values unit notes min. max. when fsc and dcl are inputs of the doc (and of the elic) (elic0:cmd1:css = 1 and ccsel1[0,2] = 11) clock period t cp 240 ns clock frequency < 4096 khz 1) ) clock period low t cpl 50 ns clock period high t cph 60 ns itt10129 (ccsel1:dclf = 1) dcl (8 mhz) fsc note 1 t cp16 t cph16 t cpl16 cd16dc t gdcp t gdcpl t gdcph t cd16dc t cd16dc t gdcp t gdcpl t gdcph t cddcfs t cddcfs t cd16fs t t t t cd16fs cddcfs cddcfs clk16 (ccsel1:dclf = 1) dcl (4 mhz) cd16dc t peb 20560 electrical characteristics semiconductor group 7-25 1997-11-01 1) these parameters are relevant only when fsc and dcl are inputs of the doc. clock period t cp 120 ns clock frequency > 4096 khz 1) clock period low t cpl 30 ns clock period high t cph 30 ns frame set-up time to clock t fs 35 ns 1) frame hold time from clock t fh 54 ns 1) serial data input set-up time t s 29 ns cfi data frequency > 4096 kbit/s serial data hold time t h 55 ns serial data input set-up time t s 29 ns cfi data frequency < 4096 kbit/s serial data hold time t h 80 ns cfi-serial output delay t cdr 19 70 ns when fsc and dcl are outputs of the doc but inputs of elic0 and elic1 (elic0:cmd1:css = 1 and ccsel1[0,2] = 00) serial data input set-up time t s 50 ns cfi data frequency > 4096 kbit/s serial data hold time t h 25 ns serial data input set-up time t s 50 ns cfi data frequency < 4096 kbit/s serial data hold time t h 45 ns cfi-serial output delay t cdr 759ns when fsc and dcl are driven by elic0 (and outputs of the doc) (elic0:cmd1:css = 0) serial data input set-up time t s tbd ns cfi data frequency > 4096 kbit/s serial data hold time t h tbd ns serial data input set-up time t s tbd ns cfi data frequency < 4096 kbit/s serial data hold time t h tbd ns cfi-serial output delay t cdr tbd tbd ns table 7-16 iom ? -2 interface timing (contd) parameter symbol limit values unit notes min. max. peb 20560 electrical characteristics semiconductor group 7-26 1997-11-01 figure 7-16 iom ? -2 interface timing 1) when 8 mhz dcl is selected, the dsp clock rate is restricted to 40 mhz, to ensure proper work of the pediu. table 7-17 fscd (delayed fsc) timing parameter symbol limit values unit notes min. max. fscd hold time after output dcl falling edge t fscdh 20 ns fscd valid time after output dcl falling edge t fscdv 80 ns when dcl rate is 8 mhz and dsp clock rate is 40 mhz. 1) 150 ns when dcl rate is 4 mhz fscd width t fscdw 900 ns itt10130 1st bit of frame 2nd bit of frame 3rd bit of frame 1st bit of frame 1st bit of frame 1st bit of frame dcl fsc dd du dd du cp t t cpl t cph fh t t fh t fs fs t t cdr cdr t t s t h t cdr t s t h peb 20560 electrical characteristics semiconductor group 7-27 1997-11-01 figure 7-17 fscd timing note: 1) the only way to use fscd is when dcl and fsc are both outputs. for dcl parameters when it is used as an output see tables: , and table 7-15 . 2) fscd is activated only when fsc is an output (ccsel1:fscs = 0 or elic0:cmd1:css = 0), and when the pediu is in mode 2, 3 or 4 (4 mbit/s or 8 mbit/s) and in active mode (refer to table 7-13 , table 7-14 , table 7-15 and table 7-16 ). when fsc is configured as input, fscd is in tri-state. if fsc is configured as output and the pediu is in idle mode or is not in work mode 2, 3 or 4, fscd will be driven by constant 0 figure 7-18 channel indication (chi) timing note: 1) for dcl parameters when it is used as an output see table 7-15 . 2) for dcl parameters when it is used as an input see table 7-16 . table 7-18 channel indication (chi) timing parameter symbol limit values unit notes min. max. chi delay from dcl rising edge t chid - 5 15 ns when dcl is an output 5 30 ns when dcl is an input itt10131 dcl (output) note 1 (output) note 2 fscd ts 31 last bit ts 32 1'st bit 2'nd bit ts 32 fscdv t fscdh t fscdw t itt10132 dcl chi chid t note 1, 2 note 3 chid t peb 20560 electrical characteristics semiconductor group 7-28 1997-11-01 3) chi signal width is 8 dcl cycles when it is operated in a single clock mode (vmodr:mod[1:0] =00, 01, 10), and 16 dcl cycles when it is operated in a double clock mode (vmodr:mod[1:0] =11). for more detailes see table 7- 13 , table 7-14 , table 7-15 and table 7-16 . figure 7-19 drdy timing 7.9.3 serial interface timing table 7-19 drdy timing parameter symbol limit values unit notes min. max. drdy setup prior to dcl rising edge t drdys tbd ns when dcl is an output drdy hold time after dcl rising edge t drdyh tbd ns drdy setup prior to dcl rising edge t drdys tbd ns when dcl is an input drdy hold time after dcl rising edge t drdyh tbd ns table 7-20 serial interface timing parameter symbol limit values unit notes min. max. when sacco-b0/1 hdc is driven by an externally generated clock 1) receive data set-up t rds 24 ns receive data hold t rdh 22 ns collision data set-up t cds 9ns itt10133 dcl drdy drdyh t drdys t drdyh t t drdys peb 20560 electrical characteristics semiconductor group 7-29 1997-11-01 collision data hold t cdh 37 ns transmit data delay t xdd 19 60 ns tri-state control delay t rtd 19 70 ns clock period t cp see chapter 7.9.1 for the timing of inputs pdc2/4/8 and table 7-16 for the timing of input dcl. when the source of sacco-b0/1 is one of the next inputs: pdc8,pdc4,pdc2 or dcl. clock period low t cpl clock period high t cph strobe set-up time to clock t xss 90 t cp-41 ns strobe set-up time to clock (extended transparent mode) t xsx 40 t cp-41 ns strobe hold time from clock t xsh 41 ns transmit data delay from strobe t sdd 66 ns transmit data high impedance from clock t xcz 65 ns transmit data high impedance from strobe t xsz 55 ns tri-stste control delay from strobe t std 66 ns sync pulse set-up time to clock t ss 40 t cp-41 ns sync pulse width t sw 40 ns when sacco-b0/1 hdc is driven by an internally generated clock 2) receive data set-up t rds 49 ns receive data hold t rdh 13 ns collision data set-up t cds 35 ns collision data hold t cdh 33 ns transmit data delay t xdd 042ns tri-state control delay t rtd 048ns table 7-20 serial interface timing (contd) parameter symbol limit values unit notes min. max. peb 20560 electrical characteristics semiconductor group 7-30 1997-11-01 1) the source which drives sacco-b0/1 hdc can be pdc8, pdc4, pdc2 or dcl. anyone of these optional sources may be generated internally or may be input to the doc. the first part of the above table, is valid during the latter case. 2) the source which drives sacco-b0/1 hdc can be pdc8, pdc4, pdc2 or dcl. anyone of these optional sources may be generated internally or may be input to the doc. the second part of the above table, is valid during the former case. clock period t cp see table 7-13 , table 7-14 and table 7-15 for the timing of outputs pdc2/4/8 and dcl. when the source of sacco-b0/1 is one of the next internally generated clocks: pdc8,pdc4,pdc2 or dcl. clock period low t cpl clock period high t cph strobe set-up time to clock t xss 112 t cp-25 ns strobe set-up time to clock (extended transparent mode) t xsx 62 t cp-25 ns strobe hold time from clock t xsh 25 ns transmit data delay from strobe t sdd 46 ns transmit data high impedance from clock t xcz 44 ns transmit data high impedance from strobe t xsz 51 ns tri-stste control delay from strobe t std 46 ns sync pulse set-up time to clock t ss 61 t cp-30 ns sync pulse width t sw 70 ns table 7-20 serial interface timing (contd) parameter symbol limit values unit notes min. max. peb 20560 electrical characteristics semiconductor group 7-31 1997-11-01 figure 7-20 serial interface timing itt05865 t rds t rdh t cpl t cp t cph t rds rdh t t xdd t cds t cdh t xdd t rtd t rtd t rtd bus timing bus timing bus timing bus timing mode 1 ccr2 : rds = 1 hdca/b rxda/b rxda/b txda/b cxda/b tsca/b tsca/b mode 2 mode 1 mode 2 peb 20560 electrical characteristics semiconductor group 7-32 1997-11-01 figure 7-21 serial interface strobe timing (clock mode 1) note: 1) only applicable in point-to-point configuration if t xsh < 0. (hfs is turned off before hdc falling edge). in this case txdb becomes invalid again, tscb is set to inactive 1, and the internal counters are not incremented, so the same valid data will be shifted out again with the next hdc/hfs rising edge. 2) with rds = 1 the sampling edge is shifted 1/2 clock phase forward. the data is internally still processed with the falling edge. therefore the strobe timing is still related to the next falling edge in that case. itt09683 t xdd t xsz t xcz t xdd t sdd t xsh t xss t xsx bus timing mode 2 mode 1/ timing bus pdc2/4/8, dcl t xcz ccr2 : rds = 1 t rdh rds t rdh t rds t rtd t rtd t rtd t t rtd std t 1) 2) point to point (hdc of hfsb0 du5/ hfsb1 dd4/txdb1 txdb0 tscb0 dd5/tscb1 dd4/txdb1 txdb0 dd5/tscb1 tscb0 du4/rxdb1 rxdb0 du4/rxdb1 rxdb0 t std sacco-b0/1) peb 20560 electrical characteristics semiconductor group 7-33 1997-11-01 figure 7-22 serial interface synchronization timing (clock mode 2) 7.9.4 reset timing 1) warm reset - when the 40 mhz external crystal is already in steady state. 2) cold reset - when the 40 mhz external crystal is not yet in steady state. 3) the strap inputs are: cdb0/boot, cdb1/dbg, cdb2/rom, cdb4/urst and cdb12/seibdis. when a strap is not driven externally, it is driven internally by an internal pull-down. if a fixed external pull-up is applied on a strap, a pull-up resistor of 5 k w is required . table 7-21 reset timing parameter symbol limit values unit notes min. max. dreset -spike pulse width t resp 5ns dreset -pulse width t repw 1250 ns warm reset 1) 10 ms cold reset 2) resin-activation delay t rad 30 ns resin-deactivation delay t rdd 300 ns strap set-up time t ss 10 ns 3) strap hold time t sh 10 ns itt05867 t ss t sw hdca/b hfsa/b peb 20560 electrical characteristics semiconductor group 7-34 1997-11-01 figure 7-23 dreset and resin timing note: cdb0/boot, cdb1/dbg, cdb2/rom, cdb4/urst and cdb12/seibdis are used as straps during reset. 7.9.5 boundary scan timing table 7-22 boundary scan timing parameter symbol limit values unit notes min. max. test clock period t tcp 160 ns test clock period low t tcpl 80 ns test clock period high t tcph 80 ns tms-set-up time to tck t mss 30 ns tms-hold time from tck t msh 30 ns tdi-set-up time to tck t dis 30 ns tdi-hold time to tck t dih 30 ns tdo-valid delay from tck t dod 60 ns itt10134 resp t t repw t rad rdd t sh t ss t dreset resin note 1 cdb 0/1/2/4/12 t t peb 20560 electrical characteristics semiconductor group 7-35 1997-11-01 figure 7-24 boundary scan timing 7.9.6 dsp external memory interface timing table 7-23 program read access timing parameter symbol limit values unit notes min. max. when c load = 50 pf program access time from cdpr and cab t pacc 32.5 ns max. dsp frequency = 20 mhz 21 ns max. dsp frequency = 2 mhz 15.8 ns max. dsp frequency = 30 mhz 12.8 ns max. dsp frequency = 33 mhz 9.5 ns max. dsp frequency = 37 mhz 7.5 ns max. dsp frequency = 40 mhz itt10135 tck tms tdi tdo tcph t tcp t tcpl t mss t msh t t dih t dis dod t peb 20560 electrical characteristics semiconductor group 7-36 1997-11-01 figure 7-25 program read access timing when c load = 30 pf program access time from cdpr and cab t pacc 33.5 ns max. dsp frequency = 20 mhz 22 ns max. dsp frequency = 26 mhz 16.8 ns max. dsp frequency = 30 mhz 13.8 ns max. dsp frequency = 33 mhz 10.5 ns max. dsp frequency = 37 mhz 8.5 ns max. dsp frequency = 40 mhz parameters for production test, only cdpr delay from dtclk t cdprd 6ns cab delay from dtclk t cabd 6ns cdb set-up time prior to dtclk t cdbs 11.5 ns table 7-23 program read access timing (contd) parameter symbol limit values unit notes min. max. cdb pacc t cab cdpr dtclk t cabd cdprd t pacc t itt10136 cdbs t peb 20560 electrical characteristics semiconductor group 7-37 1997-11-01 table 7-24 external data read access timing parameter symbol limit values unit notes min. max. when c load = 50 pf data access time from cdpr , cmbr or cbr1 ) t daccr 1) 32.5 ns max. dsp frequency = 20 mhz 21 ns max. dsp frequency = 26 mhz 15.8 ns max. dsp frequency = 30 mhz 12.8 ns max. dsp frequency = 33 mhz 9.5 ns max. dsp frequency = 37 mhz 7.5 ns max. dsp frequency = 40 mhz data access time from cab 1) t dacca 1) 82.5 ns max. dsp frequency = 20 mhz 59 ns max. dsp frequency = 26 mhz 48.8 ns max. dsp frequency = 30 mhz 36.8 ns max. dsp frequency = 33 mhz 31.5 ns max. dsp frequency = 37 mhz 27.5 ns max. dsp frequency = 40 mhz peb 20560 electrical characteristics semiconductor group 7-38 1997-11-01 when c load = 30 pf data access time from cdpr , cmbr or cbr1 ) t daccr 1) 33.5 ns max. dsp frequency = 20 mhz 22 ns max. dsp frequency = 26 mhz 16.8 ns max. dsp frequency = 30 mhz 13.8 ns max. dsp frequency = 33 mhz 10.5 ns max. dsp frequency = 37 mhz 8.5 ns max. dsp frequency = 40 mhz data access time from cab 1) t dacca 1) 83.5 ns max. dsp frequency = 20 mhz 60 ns max. dsp frequency = 26 mhz 49.8 ns max. dsp frequency = 30 mhz 37.8 ns max. dsp frequency = 33 mhz 32.5 ns max. dsp frequency = 37 mhz 28.5 ns max. dsp frequency = 40 mhz 1) the values of t daccr and t dacca , which are presented in the table, above, are valid when the number of wait- states on the external data space is 0 (memconfr:dws = 0, see section 2.7.3.1 ). when dws > 0 (dws = number of data wait-states), the time which is taken by the wait-states, should be added to the appropriate tv (tv = table value = the appropriate value from the table, above). for example, when c load = 50 pf, max. dsp frequency = 40 mhz and dws = 3: t daccr = tv + dws clock-period = 7.5 + 3 25 = 82.5 ns t dacca = tv + dws clock-period = 27.5 + 3 25 = 102.5 ns table 7-24 external data read access timing (contd) parameter symbol limit values unit notes min. max. peb 20560 electrical characteristics semiconductor group 7-39 1997-11-01 figure 7-26 external ram data read access timing diagram parameters for production test, only cdpr , cmbr or cbr delay from dtclk t rd 3.5 ns cab delay from dtclk t cabd 4.5 ns cdb set-up time prior to dtclk t cdbs 11.5 ns table 7-24 external data read access timing (contd) parameter symbol limit values unit notes min. max. itt10137 clk cdpw cdpr cmbr cmbw cbr data cdb cab [0...15] [0...15] data address program address rd t daccr t cabdd t t dacca cdbs t program data c-bus program idle c-bus data w.s. w.s. idle program peb 20560 electrical characteristics semiconductor group 7-40 1997-11-01 note: the figure, above, describes a situation in which the number of wait states is 2 (memconf:dws = 2, see section 2.7.3.1 ). dws can be programmed to any value from 0 to 7, and the timing will be changed accordingly. figure 7-27 emulation mail-box read access timing diagram note: the figure, above, describes a situation in which the number of wait states is 2 (memconf:dws = 2, see section 2.7.3.1 ). dws can be programmed to any value from 0 t0 7, and the timing will be changed accordingly. itt10138 clk cdpw cdpr cmbr cmbw cbr data cdb cab [0...15] [0...15] data address program address rd t daccr t cabdd t t dacca cdbs t program data c-bus program idle c-bus data w.s. w.s. idle program peb 20560 electrical characteristics semiconductor group 7-41 1997-11-01 figure 7-28 boot rom read access timing diagram note: the figure, above, describes a situation in which the number of wait states is 2 (memconf:dws = 2, see section 2.7.3.1 ). dws can be programmed to any value from 0 t0 7, and the timing will be changed accordingly. table 7-25 external program/data write access parameter symbol limit values unit notes min. max. cdpw or cmbw width 1) t dww 1) 8ns cab set-up time prior to cdpw or cmbw 1) t das 1) 30 ns cdb set-up time prior to cdpw or cmbw 1) t dds 1) 20 ns itt10139 clk cdpw cdpr cmbr cmbw cbr data cdb cab [0...15] [0...15] data address program address rd t daccr t cabdd t t dacc cdbs t program data c-bus program idle c-bus data w.s. w.s. idle program peb 20560 electrical characteristics semiconductor group 7-42 1997-11-01 1) the values of t dww , t das and t dds which are presented in the table, above, are valid only during program write access, or during data write access, when the number of wait-states on the external data space is 0 (memconfr:dws = 0, see section 2.7.3.1 ). for data write access timing, when dws > 0 (dws = number of data wait-states), the time which is taken by the wait-states, should be added to the appropriate tv (tv = table value = the appropriate value from the table, above). for example, when dws = 3: t dww = tv + dws clock-period = 8 + 3 25 = 83 ns t das = tv + dws clock-period = 30 + 3 25 = 105 ns t dds = tv + dws clock-period = 20 + 3 25 = 95 ns cab hold time from cdpw or cmbw t dah 5ns cdb hold time from cdpw or cmbw t ddh 4ns parameters for production test, only cdb delay from dtclk t ddd 20 ns cab delay from dtclk t dad 10 ns cdpw or cmbw delay from dtclk t dwd 6ns cab hold time from dtclk t dahc 0ns cdb hold time from dtclk t ddhc 10 ns table 7-25 external program/data write access parameter symbol limit values unit notes min. max. peb 20560 electrical characteristics semiconductor group 7-43 1997-11-01 figure 7-29 external data write access note: the figure, above, describes a situation in which the number of wait states is 2 (memconf:dws = 2, see section 2.7.3.1 ). dws can be programmed to any value from 0 t0 7, and the timing will be changed accordingly. itt10140 clk cdpw cdpr cmbr cmbw cbr data cdb cab [0...15] [0...15] data address program address dwd t dww t dad t program data dahc t das t t dah ddhc t t ddh t dds ddd t dwd t c-bus program idle c-bus data w.s. w.s. idle program peb 20560 electrical characteristics semiconductor group 7-44 1997-11-01 figure 7-30 emulation mail-box write access note: the above figure describes a situation in which the number of wait states is 2 (memconf:dws = 2, see section 2.7.3.1 ). dws can be programmed to any value from 0 t0 7, and the timing will be changed accordingly. itt10141 clk c-bus program data c-bus idle idle w.s. w.s. cdpw cdpr cmbr cmbw cbr data cdb cab [0...15] [0...15] data address program address dwd t dww t dad t program data dahc t das t t dah ddhc t t ddh t dds ddd t dwd t program peb 20560 electrical characteristics semiconductor group 7-45 1997-11-01 . figure 7-31 external program write access due to movd note: movd write cycle does not include any wait states, at all. 7.9.7 clocks signals timing (additional to the iom ? -2 and pcm clocks) table 7-26 clk61 (input) timing parameter symbol limit values unit notes min. max. clk61 clock period t c61cp 16 ns 61.44 mhz clk61 clock period low t c61cpl 5ns clk61 clock period high t c61cph 5ns itt10142 written data write address clk cdpr cdpw cab[0...15] cdb[0...15] program read write program read program idle1 idle2 dwd t dwd t t dad t dahc t dww das t t dah ddd t dds t t ddh ddhc t peb 20560 electrical characteristics semiconductor group 7-46 1997-11-01 figure 7-32 clk61 (input) timing figure 7-33 clk16 (input) timing table 7-27 clk16 (input) timing parameter symbol limit values unit notes min. max. clk16 clock period t c16cp 61 ns 16.384 mhz clk16 clock period low t c16cpl 20 ns clk16 clock period high t c16cph 20 ns table 7-28 refclk timing parameter symbol limit values unit notes min. max. when refclk is used as an input refclk clock period t rcp 125 m s 8 khz 1953 ns 512 khz 651 ns 1536 khz 488 ns 2048 khz refclk clock period low t rcpl 150 ns refclk clock period high t rcph 150 ns itt10143 clk61 c61cph t c61cp t c61cpl t itt10144 clk16 c16cph t c16cp t c16cpl t peb 20560 electrical characteristics semiconductor group 7-47 1997-11-01 figure 7-34 refclk timing figure 7-35 xclk (input) timing when refclk is used as an output refclk clock period t rcp 125 m s 8 khz 1953 ns 512 khz refclk clock period low t rcpl 100 ns refclk clock period high t rcph 100 ns table 7-29 xclk (input) timing parameter symbol limit values unit notes min. max. xclk clock period t xcp 125 m s 8 khz 1953 ns 512 khz 651 ns 1536 khz 488 ns 2048 khz xclk clock period low t xcpl 150 ns xclk clock period high t xcph 150 ns table 7-28 refclk timing parameter symbol limit values unit notes min. max. itt10145 refclk rcph t rcp t rcpl t itt10146 xclk xcph t xcp t xcpl t peb 20560 electrical characteristics semiconductor group 7-48 1997-11-01 figure 7-36 clk30 (output) timing figure 7-37 clk15 (output) timing table 7-30 clk30 (output) timing parameter symbol limit values unit notes min. max. clk30 clock period t cp30 32 ns 30.72 mhz when clk61 = 61.44 mhz clk30 clock period low t cpl30 10 ns clk30 clock period high t cph30 10 ns table 7-31 clk15 (output) timing parameter symbol limit values unit notes min. max. clk15 clock period t cp15 65 ns 15.36 mhz when clk61 = 61.44 mhz clk15 clock period low t cpl15 20 ns clk15 clock period high t cph15 20 ns itt10147 clk30 cph30 t cp30 t cpl30 t itt10148 clk15 cph15 t cp15 t cpl15 t peb 20560 electrical characteristics semiconductor group 7-49 1997-11-01 figure 7-38 clk7 (output) timing table 7-32 clk7 (output) timing parameter symbol limit values unit notes min. max. clk7 clock period t cp7 130 ns 7.68 mhz when clk61 = 61.44 mhz clk7 clock period low t cpl7 40 ns clk7 clock period high t cph7 40 ns itt10149 clk7 cph7 t cp7 t cpl7 t peb 20560 ordering information and mechanical data semiconductor group 8-1 1997-11-01 8 ordering information and mechanical data 8.1 package outlines figure 8-1 package outline sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device p-mqfp-160-1 (plastic metric quad flat package) gpm05247 peb 20560 appendix semiconductor group 9-1 1997-11-01 9 appendix 9.1 iom ? -2 interface this standardized interface for interchip communication in isdn line cards for digital exchange systems was developed by the group of four (alcatel, siemens, plessey and italtel systems companies). the iom-2 interface is a four-wire interface with a bit clock, a frame clock and one data line per direction. it has a flexible data clock. this way, data transmission requirements are optimized for different applications. figure 9-1 iom ? -2 interface with 4-bit c/i channel 9.1.1 signals / channels fsc frame synchronization clock, 8 khz dcl data clock, 2.048 or 4.096 mhz dd data downstream, 2.048 mbit/s (4.096 mbit/s) du data upstream, 2.048 mbit/s (4.096 mbit/s) monitor monitor channel d signaling channel, 16 kbit/s c/i command/indication channel mr monitor receive handshake signal mx monitor transmit handshake signal itd04319 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 b1 b2 monitor d c/i mm rx fsc dcl du dd ch0 ch0 s 125 r iom r iom peb 20560 appendix semiconductor group 9-2 1997-11-01 9.1.2 monitor and c/i handlers the epic also supports the monitor and command/indication (c/i) channels in accordance with the iom-2 interface protocol. the monitor handler controls the data flow on the monitor channel either with or without an active handshake protocol. to reduce the dynamic load of the m p, a 16-byte transmit/receive fifo is provided. the c/i handler supports different schemes: in downstream direction the relevant content of the control memory (= command) is transmitted in the appropriate time-slot. in upstream direction the c/i handler monitors the received data (= indication). upon a change it generates an interrupt, stores the channel address in the 9-byte deep c/i-fifo and the actual c/i value in the control memory. double last-look check is provided. a 7-bit hardware timer can be used to interrupt the m p or dsp cyclically to determine the double last-look period. for more details please refer to iom-2 interface reference guide 3.91 9.1.3 iom ? -2 interface timing figure 9-2 iom ? -2 interface timing with single data rate dcl t fs fwh t fh t t fwl t fs ds t ddc t dh t fsc(i) dcl(i) id i id o itd06879 t dcl lost channels (...,b*-channel) first channel (b1,channel,...) frame n r iom -2 frame n+1 iom -2 r peb 20560 appendix semiconductor group 9-3 1997-11-01 figure 9-3 timing of the iom ? -2 interface with double data rate dcl 1) t ddf = 0.5 t dcl + t ddc - t fh table 9-1 timing characteristics of the iom ? -2 parameter symbol limit values unit condition min. typ. max. frame sync. hold t fh 30 ns frame sync. setup t fs 70 ns frame sync. high t fwh 130 ns frame sync. low t fwl t dcl data delay to clock t ddc 100 ns data delay to frame 1) t ddf 150 ns data setup t ds 20 ns data hold t dh 50 ns t fs fwh t fh tt fh t fwl t fs ds t ddc t dh t lost channels (...,b*-channel) first channel (b1,channel,...) fsc(i) dcl(i) id i id o itd06878 frame n dcl t r iom -2 frame n+1 iom -2 r peb 20560 appendix semiconductor group 9-4 1997-11-01 9.2 working sheets for multiplexers programming 9.3 working sheets the following pages contain working sheets to facilitate the programming of the doc incl. epic-1. for several tasks (i.e. initialization, time-slot switching, ) the corresponding registers are summarized in a way the programmer gets a quick overview on the registers he has to use. ? register summary for epic initialisation ? switching of pcm time-slots to the cfi interface (data downstream) ? switching of cfi time-slots to the pcm interface (data upstream) ? preparing epics c/i channels ? recieving and transmitting iom-2 c/i codes ? doc port and signaling multiplexers ? doc clocking multiplexers 1) t ddf = 0.5 t dcl + t ddc - t fh table 9-2 timing characteristics of the iom ? -2 parameter symbol limit values unit condition min. typ. max. frame sync hold t fh 30 ns frame sync setup t fs 70 ns frame sync high t fwh 130 ns frame sync low t fwl t dcl data delay to clock t ddc 100 ns data delay to frame 1) t ddf 150 ns data setup t ds 20 ns data hold t dh 50 ns peb 20560 appendix semiconductor group 9-5 1997-11-01 9.3.1 register summary for epic ? initialization figure 9-4 a epic ? initialization register summary (working sheet) pcm interface pmod pcm mode register rw, 20 h (0 h + rbs = 1), reset-val. = 00 pmd0 1 = pcm mode, 00 = 0, 01 = 1, 10 = 2 pcr = pcm clock rate: 0 = equal to pcm data rate 1 = double pcm data rate (not for mode 2) psm = pcm synchron mode: 0 = frame synchr. with falling edge, 1 = rising edge of pdc ais0 1 = alternative input section: (pcm mode dependent) mode 0: ais = 0 mode 1: ais0 = 0: rxd1 = in0, ais0 = 1: rxd0 = in0 ais1 = 0: rxd3 = in1, ais1 = 1: rxd2 = in1 mode 2: ais0 = 0 ais1 = 0: rxd3 = in, ais = 1: rxd2 = in aic0 1 = alternative input comparison: (pcm mode dependent) mode 0, 1: aic0 = 0: no comparison, aic0 = 1: rxd0 == rxd1 aic1 = 0: no comparison, aic1 = 1: rxd2 == rxd3 mode 2: aic0 = 0: aic1 = 0: no comparison, aic1 = 1: rxd2 == rxd3 pbnr pcm bit number register rw, 22 h (1 h + rbs = 1), reset-val. = ff bnr0 7 = bit number per frame (mode dependent) mode 0: bnr = number of bits C 1 mode 1: bnr = (number of bits)/2 C 1 mode 2: bnr = (number of bits)/4 C 1 note: rxdx relate to internal elic ports pmd pcr psm ais aic bnr peb 20560 appendix semiconductor group 9-6 1997-11-01 figure 9-4b epic ? initialization register summary (working sheet) pofd pcm offset downstream register rw, 24 h (2 h + rbs = 1), reset-val. = 0 ofd2 9 = offset downstream (see pcsr for ofd0 1) mode 0: (bnd C 17 + bpf) mod bpf --> ofd2 9 mode 1: (bnd C 33 + bpf) mod bpf --> ofd1 9 mode 2: (bnd C 65 + bpf) mod bpf --> ofd0 9 bnd = number of bits + 1 that the downstream frame start is left shifted relative to the frame sync bpf = number of bits per frame unused bits must be set to 0 ! pofu pcm offset upstream register rw, 26 h (3 h + rbs = 1), reset-val. = 0 ofu2 9 = offset upstream (see pcsr for ofu0 1) mode 0: (bnd + 23 + bpf) mod bpf --> ofu2 9 mode 1: (bnd + 47 + bpf) mod bpf --> ofu1 9 mode 2: (bnd + 95 + bpf) mod bpf --> ofu0 9 bnd = number of bits + 1 that the upstream frame is left shifted relative to the frame start bpf = number of bits per frame unused bits must be set to 0 ! pcsr pcm clock shift register rw, 28 h (4 h + rbs = 1), reset-val. = 0 ofd0 1 = offset downstream (see pofd) dre = downstream rising edge, 0 = receive data on falling edge, 1 = receive data on rising edge ofu0 1 = offset upstream (see pofu) ure = upstream rising edge, 0 = send data on falling edge, 1 = send data on rising edge ofd9..2 ofu9..2 0 ofd1 0 dre 0 ofu1 0 ure peb 20560 appendix semiconductor group 9-7 1997-11-01 figure 9-4c epic ? initialization register summary (working sheet) cfi interface cmd1 cfi mode register 1 rw, 2c h (6 h + rbs = 1), reset-val. = 00 css = clock source select, 0 = pdc/pfs used for cfi, 1= dcl/fsc are inputs csm = cfi synchronization mode: 1 = frame syncr. with rising edge, 0 = falling edge of dcl if css = 0 ==> cmd1:csm = pmod:psm ! csp0 1 = clock source prescaler: 00 = 1/2, 01 = 1/1.5, 10 = 1/1 cmd0 1 = cfi mode: 00 = 0, 01 = 1, 10 = 2, 11 = 3 cis0 1 = cfi alternative input section mode 0, 3: cis0 1 = 0 mode 1, 2: cis0: 0 = in0 = du0, 1 = in0 = du2 mode 1: cis1: 0 = in1 = du1, 1 = in1 = du3 cmd2 cfi mode register 2 rw, 2e h (7 h + rbs = 1), reset-val. = 00 for iom ? -2 cmd2 can be set to d0 h fc0 2 = framing signal output control (cmd1:css = 0) = 010 suitable for pbc, = 011 for iom-2, = 110 iom-2 and sld coc = clock output control (cmd1:css = 0) = 0 dcl = data rate, = 1 dcl 2 data rate (only mode 0 and 3 !) cxf = cfi transmit on falling edge: 0 = send on rising edge, 1 = send on falling dcl edge crr = cfi receive on rising edge: 0 = receive on falling edge, 1 = send on rising dcl edge cbn8 9 = cfi bit number (see cbnr) cbnr cfi bit number register rw, 30 h (8 h + rbs = 1), reset-val. = ff cbn0 7 = cfi bit number per frame C 1 (see cmd2:cbn8 9) css csm csp1 0 cmd1 0 cis1 0 fc2 0 coc cxf crr cbn9 8 cbn peb 20560 appendix semiconductor group 9-8 1997-11-01 figure 9-4d epic ? initialization register summary (working sheet) ctar cfi time-slot adjustment register rw, 32 h (9 h + rbs = 1), reset-val. = 00 tsn0 6 = (number of time-slots + 2) the du and dd frame is left shifted relative to frame start (see also cbsr) cbsr cfi bit shift register rw, 34 h (a h + rbs = 1), reset-val. = 00 cds2 0: cfi downstream/upstream bit shift shift du and dd frame: 000 = 2 bits right 001 = 1 bit right 010 = 6 bits left 011 = 5 bits left 100 = 4 bits left 101 = 3 bits left 110 = 2 bits left 111 = 1 bit left relative to pfs (if cmd1:css = 0) relative to fsc (if cmd1:css = 1) cscr cfi subchannel register rw, 36 h (a h + rbs = 1), reset-val. = 00 sc3 0 1 control port 3 (+ port 7 for cfi mode 3 (sld)) sc2 0 1 control port 2 (+ port 6 for cfi mode 3 (sld)) sc1 0 1 control port 1 (+ port 5 for cfi mode 3 (sld)) sc0 0 1 control port 0 (+ port 4 for cfi mode 3 (sld)) for 64 kbit/s channel: 00/01/10/11 = bits 7 0 for 32 kbit/s channel: 00/10 = bits 7 4, 01/11 = bits 3 0 0 tsn 0 cds2 0 cus3 0 cs3 cs2 cs1 cs0 peb 20560 appendix semiconductor group 9-9 1997-11-01 9.3.2 switching of pcm time-slots to the cfi interface (data downstream) figure 9-5 switching of pcm time-slots to the cfi interface (working sheet) itd08110 data memory pcm ts elic, r epic r 0....... maar cfi port, ts madr . . . . . . . . pcm port, ts switching command 01110001 macr switching of 8 bit channels: 1 10= 1 1 = 7, 6 0010= = 1 1 0 0 macr . . . . 1 1 1 0 ........ madr maar . . . . . . . 0 = 1 0 00= 5, 4 3, 2 1, 0 loop 0 output disable cfi ts loop direct switching of subchannels: 01 01 01 01 switched ts width and pcm bit position ........ cscr 3 2 1 0 cfi port 0 0 = 7 ... 4 or 7, 6 (default for d channel) = 01 = 10 = 11 cfi bit position writing 8 bit cfi idle codes by the mp : macr 1 0 0 1 1 1 1 0 write value to cm data value of idle code (w) ........ madr maar . . . . . . . 0 0....... maar madr . . . . . . . . value of idle code (r) read value to cm data 11001000 macr reading back a previously written 8 0....... maar select 01111001 macr reading pcm data switched to cfi: 0....... maar madr . . . . . . . . value (r) read data memory: 1....000 macr position and bit ts width desired tristating a cfi output ts: 0....... maar 01110000 macr port maar . . . . . x madr ts ts madr x.... .. maar . . . . . . x ts ts madr x....... maar p access switching command p access cfi + pcm mode 0 pcm mode 1 cfi mode 1 cfi + pcm mode 2 . for madr/maar setings see loewr box for madr/maar setings see loewr box . cfi port, ts pcm port, ts ... ... 3 ... 0 or 5, 4 ... 7 ... 4 or 3, 2 ... 3 ... 0 or 1, 0 ... 7 ... 4 3 ... 0 ... . for maar setings see lower box cfi port, ts cfi port, ts pcm port, ts pcm port, ts bit cfi idle codes by the mp : cfi port, ts 3 ... 0 7 ... 4 1 0 1 0 1 0 1 0 1, 0 3, 2 5, 4 = 0 0 01= 0011= = 0 1 0 0 7, 6 = 1 1 = 0 1 = 1 0 0 0 7 ... 0 port port select p access . ... note : port relates to internal elic ports peb 20560 appendix semiconductor group 9-10 1997-11-01 9.3.3 switching of cfi time-slots to the pcm interface (data upstream) figure 9-6 switching of cfi time-slots to the pcm interface (working sheet) itd08111 data memory pcm ts elic, r epic r 1....... maar cfi port, ts madr . . . . . . . . pcm port, ts switching command 01110001 macr switching of 8 bit channels: 10= 1 1 = 7, 6 0010= = 1 1 0 0 macr . . . . 1 1 1 0 ........ madr maar . . . . . . . 1 = 1 0 00= 5, 4 3, 2 1, 0 loop cfi ts loop direct switching of subchannels: 01 01 01 01 switched ts width and pcm bit position ........ cscr 3 2 1 0 cfi port 0 0 = 7 ... 4 or 7, 6 (default for d channel) = 01 = 10 = 11 cfi bit position enable/tristate pcm output ts: macr 0 0 0 command select bit position .... madr maar . . . . . . . 1 writing/reading back pcm idle codes and reading switched cfi data: 1....... maar madr . . . . . . . disable switching connection 0111 000 macr position and bit ts width desired reading a cfi ts by the mp (no connection to pcm): 1....... maar 0111 00 macr port maar . . . . . x madr ts ts madr x.... .. maar . . . . . . x ts ts madr x....... maar p access switching command access p select cfi + pcm mode 0 pcm mode 1 cfi mode 1 cfi + pcm mode 2 . for madr/maar setings see loewr box for madr/maar setings see loewr box . cfi port, ts pcm port, ts 3 ... 0 or 5, 4 7 ... 4 or 3, 2 3 ... 0 or 1, 0 7 ... 4 3 ... 0 . for maar setings see lower box cfi port, ts 3 ... 0 7 ... 4 1 0 1 0 1 0 1 0 1, 0 3, 2 5, 4 = 0 0 01= 0011= = 0 1 0 0 7, 6 = 1 1 = 0 1 = 1 0 0 0 7 ... 0 1 0 enable/ disable pcm port, ts 1111 . . . . 7, 6 3, 2 1, 0 4, 5 0 0 = tristate 1 = driver enabled 1 0 = one ts 0 0 1 = 1 1 = all ts 1 pcm port, ts macr 0 0 0 . . . . read/write data memory value or idle code ........ madr maar . . . . . . . 1 cfi port, ts pcm port, ts 1 0 . = 1 = read cfi value 0 = write idle code read back idle code for writing idle codes, connection to neccessary only exists! pcm ts already if a for maar setings see lower box . madr . . . . . . . . ts value (r) 11 cfi port, ts maar . . . . . . . 1 1 macr 0 0 10 read value to cm data 00 1 port port . . . . note : port relates to internal elic ports peb 20560 appendix semiconductor group 9-11 1997-11-01 9.3.4 preparing epics c/i channels figure 9-7 preparing epic ? s c/i channels (working sheet) itd08112 b/d c/i-fifo cm data pointer data memory pcm ts elic, r epic r cfi mode 0 iom -2 r 0...1..0 maar port iom -2 channel r madr 1 1 . . . . . . c/i idle code mode selection 0111.... macr 1 1 4 bit c/i 6 bit c/i initialization of the c/i channels data downstream: d c/i 1 0 0 0 = decentral central = 0 1 0 1 = 0 1 0 1 elic sacco-a = 0 1 0 1 6 bits analog c/i 10= 1 1 = pcm ts bit 7, 6 01xx= = 1 1 0 1 macr . . . . 1 1 1 0 mode selection pcm port, ts 0....... madr port maar 1 . . 1 . . . 0 = 1 0 00= 1 0 1 1 = analog c/i = 1 1 0 1 r r elic sacco-a only for central d channel handling ! elic sacco-a r r 0000= analog c/i = 0 1 0 1 = 0 0 01= 1...1..1 maar port madr . . . . . . . 1 pcm port, ts mode selection 0111.... macr 0000= = x x 1 0 pcm ts bit 7, 6 = 1 1 = 0 1 6 bit analog c/i 1 0 0 0 = elic sacco-a 1010= 1000= = 0 0 0 1 initialization of the c/i channels data upstream: expected c/i-value macr . . . . 1 1 1 0 mode selection c/i idle code ......11 madr port maar 0 . . 1 . . . 1 expectend c/i value ......11 madr only analog 6 bit c/i handling ! r iom -2 channel d channel handling d channel handling d channel handling d channel handling central decentral d channel handling ! only for central decentral central d channel handling d channel handling decentral central d channel handling d channel handling d channel handling d channel handling d channel handling iom -2 channel r pcm ts bit 5, 4 pcm ts bit 3, 2 pcm ts bit 1, 0 iom -2 channel r pcm ts bit 5, 4 pcm ts bit 3, 2 pcm ts bit 1, 0 peb 20560 appendix semiconductor group 9-12 1997-11-01 9.3.5 receiving and transmitting iom ? -2 c/i-codes figure 9-8 receiving and transmitting iom ? -2 c/i-codes (working sheet) itd08113 0...1..0 maar port iom -2 channel r madr 1 1 . . . . . . c/i value (w) write command 01001000 macr 1 1 4 bit c/i 6 bit c/i value transmitting a c/i code on iom -2 data downstream: receiving a c/i code on iom -2 data upstream: c/i-fifo 1. ... 2. ... 3. ... iom -2 frame r b1 b2 m c/i b1 b2 m c/i r iom -2 channel c/i change detected interrupt : ista : sfi read cfifo and copy value to maar 6 bit c/i value 4 bit c/i value macr 0 0 0 1 0 0 1 1 read command c/i value (r) ......11 madr c/i fifo port maar . . 1 . . . 1 c/i d r iom -2 cfi mode 0 r epic r elic, pcm ts data memory pointer cm data c/i-fifo r r iom -2 channel r 4 bit c/i value : 0 6 bit c/i value : 1 note : port relates to internal elic ports peb 20560 appendix semiconductor group 9-13 1997-11-01 9.3.6 doc port and signaling multiplexers figure 9-9 its10150 sidec0 sidec1 sidec2 sidec3 sacco-b0 sacco-b1 rxd/txd rxd/txd rxd/txd rxd/txd rxd/txd txd/rxd r iom signaling mux mcchsel0 mcchsel0 mcchsel1 mcchsel1 mcchsel2 mcchsel2 0: disabled 1: enabled 0: txd/rxd connected to dd/du 1: txd/rxd connected to du/dd port number (0...3) sacco-a0 dd0 du0 dd1 du1 dd3 du3 dd2 du2 txd0 rxd0 txd1 rxd1 txd2 rxd2 txd3 rxd3 el0 du3 dd3 rxd3 txd3 sacco-a1 du2 dd2 du1 dd1 dd0 du0 rxd2 txd2 rxd0 txd0 el1 rxd1 txd1 2 elic -1 mux r 1 0 0 0 0 txd/rxd dd0/du0 dd1/du1 dd2/du2 dd3/du3 dd4/du4 dd5/du5 dd6/du6 dd7/du7 mmode 0 00 0 2 1 2 1 2 1 mux iom r tscb1/hfsb1 cxdb1/drqtb1 drqrb1/dackb1 0 1 1 1 1 1 1 pcm mux pcm signaling 0 0 0 sacco-b0 sacco-b1 rxd0/txd0 rxd1/txd1 rxd2/txd2 rxd3/txd3 mpchsel0 mpchsel0 drqrb0 drqtb0 dackb0 hfsb0 0 0000 vcfgr iop0 iop1 iop2 iop3 txdb0/rxdb0 el0_tsc0 or el1_tsc0 or tsc sacco_b el0_tsc0 or tsc sacco_b el0_tsc1 or el1_tsc1 or tsc sacco_b el1_tsc1 or tsc sacco_b el0_tsc2 or el1_tsc2 or tsc sacco_b el0_tsc2 or tsc sacco_b el1_tsc3 or tsc sacco_b el0_tsc3 or el1_tsc3 or tsc sacco_b port number (0...3) 1: txd/rxd connected to rxd0/txd 0: txd/rxd connected to txd0/rxd 1: enabled 0: disabled mux doc port and signaling multiplexer 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 peb 20560 appendix semiconductor group 9-14 1997-11-01 9.3.7 doc clocking multiplexers figure 9-10 its10151 :3 10 :4 11 00 01 10 11 ccsel2 00 internal 1 0 phase comp. 0 1 refclk xclk vcxo 512 khz 8 khz elic -0 r fsc dcl sacco-b0 b) a) c) sacco-b1 d) f) e) pdc pfs elic r -1 hdc hdc 10 11 01 00 11 10 01 00 pdc pfs 10 01 00 dcl0 dcl0 0 1 internal 8 mhz pdc8 internal 8 khz 1 0 pfs internal 4 mhz internal 2 mhz 0 1 0 pdc2 pdc4 1 ccsel1 0 ccsel0 0 0 0 1 pdc8 pdc4 ccsel1 elic -0:cmd1 1 0 0 1 real time clock 0 10 ms 1 10 s dsp frequency (read only) 00 20 mhz 00 30 mhz 10 40 mhz 11 61 mhz a) b) c) d) e) f) xxxx 1xxx mcchsel2 mpchsel0 xxxx 0xxx xxxx 0xxx xxxx 1xxx xxxx 0xxx xxxx 0xxx 1xxx xxxx 0xxx xxxx 0xxx xxxx 1xxx xxxx 1xxx xxxx 0xxx xxxx 512 khz internal 8 khz r fsc0 dcl0 00 0 1 0 1 dcl0 peb 20560 appendix semiconductor group 9-15 1997-11-01 9.4 development tools and software support 9.4.1 software the software development tools help to minimize the time to market and development costs. the software consists of: macro assembler, linker/locator, object format converter, ansii c compiler, simulator with a debugger for ocem. all dsp software development tools can operate on microsoft. 9.4.2 macro assembler the macro assembler translates dsp assembly language source files into dsp machine language object files. it consists of a macro preprocessor which checks dsp programming restrictions and prepares the object for full symbolic debugging. it contains c-like operators and conventions that allow easy development of code and data structures. the object files generated are compatible to the common object file format (coff). 9.4.3 linker/locator the linker/locator combines object files generated by the coff macro assembler into a single executable coff object file. as it creates the executable object file, it performs relocation which means map them to the target systems memory map. it also supports user defined memory classes and enables to locate segments to absolute locations or relative to other segments and to overlay segments. its linking capability is very flexible and modular. 9.4.4 c compiler the c cross compiler is a state-of-the-art compiler providing 2 options for genrating efficient dsp object code: 1. to mix object files generated by the compiler with those generated by the assembler directly from efficient hand coded assembly instructions, 2. to use dsp specific c language extensions. 9.4.5 object format converter most eprom programmers do not accept executable coff object files as input. therefore the object format converter translates the coff file into intel hex file format that can be downloaded to any ordinary eprom programmer. 9.4.6 simulator the simulator simulates the operation of the dsp for program verification and debugging purposes. it simulates the entire dsp instruction set and accepts executable peb 20560 appendix semiconductor group 9-16 1997-11-01 coff object code generated from the linker/locator. the simulator allows verification and monitoring of the dsp states without the requirement of the dsp hardware. besides a windowed mouse driven interface which can be user-customized it also contains a high level language debug interface. to simulate external signals or hardware logic, it is possible to connect dos files and integrate c functions using the dynamic link library (dll) mechanism of windows. during program execution, the internal registers and memory of the simulated dsp are modified as each instruction is interpreted by the host. execution is suspended when either a breakpoint or an error is encountered or when the user halts execution. then the dsp internal registers and both program and data memory can be inspected and modified. 9.5 oak development / evaluation board siemens provides a development board which can be used for a quick start for a new project; to develop software, test interfaces, memory configuration, critical ics, etc. both, the microprocessor and the dsp can be controlled at a time via two different serial interfaces, figure 9-11 . figure 9-11 doc evaluation board - block diagram thus the software development engineers can interactively read from and write to all doc registers. the doc evaluation board, figure 9-12 , implements the full hardware functionality of a small pbx and supports many features of the doc within an intel 386ex based microprocessor system enviroment. with the doc board siemens will also offer a pbx orientedand basic software modules. itb10242 sicofi -4 r r -s quat r -p octat doc doc user board message 80386-ex m bootloader handler p gik 386sx jtag data bus m p debugging pc 2 pc 1 dsp debugging peb 20560 appendix semiconductor group 9-17 1997-11-01 figure 9-12 doc evaluation system as the development board differs from the target application the user software must be ported to the final hardware. different dsp software and development tools can be provided for the following pc operating systems: windows 3.1, windows 95 and windows nt. ita10243 peb 20560 appendix semiconductor group 9-18 1997-11-01 9.6 doc configurator the doc configurator is a configuration tool, that helps the user to determine the initialization register values for the doc (peb 20560). the expert system asks the user questions about the desired functionality by offering a valid range of parameters (options). it helps to avoid wrong choices and insures a valid system description. the configurator then automatically provides: 1. a register map (file: reg_map.h) with all the addresses in c convention 2. an initialization sequence in visual c++ (library file) with all necessary register values for initialization 3. a ready to run track file for the evaluation package, sipb 20560. the following two figures show screen examples of the windows based configurator: figure 9-13 example for sidecs and saccos assignment peb 20560 appendix semiconductor group 9-19 1997-11-01 figure 9-14 example for selection of elic clocks note: the doc configurator runs at any standard pc. peb 20560 acronym semiconductor group 10-1 1997-11-01 10 acronym a ale address latch enable asm arbiter state machine b b-channel 64 kbit/s voice and data channel c c/i command/indication ccitt comit consultativ international tlgraph et tlphone cfi configurable interface co central office codec coder/decoder cpu central processing limit crc cyclic redundancy check cv code violation d d-channel 16 kbit/s packetized (p) data and control (s) dcl data clock dd data downstream dma direct memory access ds data strobe signal dsp digital signal processor dte data terminal equipment du data upstream e elic extended line card interface controller eom end of transmission epic extended pcm interface controller et exchange termination etsi european telecommunications standardization institute f fcs frame check sequence fifo first in first out fsc frame synchronization clock peb 20560 acronym semiconductor group 10-2 1997-11-01 g gci general circuit interface h hdlc high level data link control procedure hscx high level serial communications controller extended i ibc isdn burst controller idec isdn d channel exchange controller isdn integrated service digital network iec-q isdn echo cancellation circuit conforming to 2b/1q line code iepc isdn exchange power controller iom isdn oriented modular interface isac-s isdn subscriber access controller for s/t bus iso international standard organization l lap-b link access procedure on b-channel lap-d link access procedure on d-channel lt line termination lt-s line termination on s-interface lt-t line termination on t-interface m md monitor data mr monitor receive handshake signal mux multiplexer mx monitor transmit handshake signal n nt network termination p pbx private branch exchange pbc peripheral board controller pcm pulse code modulation pll phase locked loop q quat-s quadruple transceiver for sit-interfaces peb 20560 acronym semiconductor group 10-3 1997-11-01 r res reset rd/wr read/write rxd receive data s scc serial communication controller s-interface ccitt i.430, 4-wire int. for up to 8 isdn terminals s/t-interface subscriber/trunk interface sacco special application-communication controller sbcx s/t bus interface circuit extended sicofi signal processing codec/filter slic subscriber line interface controller t te terminal equipment tsa time-slot assignment t d transmit data u u-interface 2-wire ping-pong connection |
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